Home
last modified time | relevance | path

Searched refs:dmult (Results 1 – 25 of 37) sorted by relevance

12

/external/llvm/test/CodeGen/Mips/
Dmips64muldiv.ll14 ; ACC: dmult ${{[45]}}, ${{[45]}}
31 ; ACC: dmult $4, $[[T0]]
Docteon.ll22 ; MIPS64: dmult $4, $5
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dmul.ll200 ; M4: dmult $4, $5
203 ; 64R1-R5: dmult $4, $5
233 ; GP64-NOT-R6: dmult $4, $7
235 ; GP64-NOT-R6: dmult $5, $6
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3-wrong-error.s9 … dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips4.s24 …dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Mips/
Delf-gprel-32-64.s51 dmult $3, $4
Ddo_switch3.s43 dmult $2, $3
/external/valgrind/none/tests/mips64/
Darithmetic_instruction.stdout.exp-mips6410473 dmult $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
10474 dmult $v0, $v1 :: rs 0x12bd6aa, rt 0xa2a6ec661ba84121, HI 0xffffffffff92aaaf, LO 0xa7b8a47115b7d5ea
10475 dmult $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
10476 dmult $v0, $v1 :: rs 0x7e876382d2ab13, rt 0x614d9b445f12236b, HI 0x3017a82b446008, LO 0xe93183d28fc…
10477 dmult $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0xffffffffffffffff, LO 0xfd57bc67e4ba75ac
10478 dmult $v0, $v1 :: rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75, HI 0xe7a0888c77592cc1, LO 0xe923a4d…
10479 dmult $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xffffffffffffffff, LO 0xfc83823413a60065
10480 dmult $v0, $v1 :: rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666, HI 0xe283ab72304992dd, LO 0x218872f…
10481 dmult $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0xffffffffffffffff, LO 0xf9166da2b5b6b160
10482 dmult $v0, $v1 :: rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17, HI 0x172a574aa8a55dea, LO 0x228b272…
[all …]
Darithmetic_instruction.stdout.exp-mips64r210473 dmult $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
10474 dmult $v0, $v1 :: rs 0x12bd6aa, rt 0xa2a6ec661ba84121, HI 0xffffffffff92aaaf, LO 0xa7b8a47115b7d5ea
10475 dmult $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
10476 dmult $v0, $v1 :: rs 0x7e876382d2ab13, rt 0x614d9b445f12236b, HI 0x3017a82b446008, LO 0xe93183d28fc…
10477 dmult $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0xffffffffffffffff, LO 0xfd57bc67e4ba75ac
10478 dmult $v0, $v1 :: rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75, HI 0xe7a0888c77592cc1, LO 0xe923a4d…
10479 dmult $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xffffffffffffffff, LO 0xfc83823413a60065
10480 dmult $v0, $v1 :: rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666, HI 0xe283ab72304992dd, LO 0x218872f…
10481 dmult $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0xffffffffffffffff, LO 0xf9166da2b5b6b160
10482 dmult $v0, $v1 :: rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17, HI 0x172a574aa8a55dea, LO 0x228b272…
[all …]
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips3.s12 …dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips64.s16 …dmult $s7,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-el.txt89 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
229 0x1c 0x00 0x7a 0x01 # CHECK: dmult $11, $26
Dvalid-mips64.txt102 0x01 0x7a 0x00 0x1c # CHECK: dmult $11, $26
123 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-mips64r2-el.txt95 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
250 0x1c 0x00 0x7a 0x01 # CHECK: dmult $11, $26
Dvalid-mips64r2.txt114 0x01 0x7a 0x00 0x1c # CHECK: dmult $11, $26
136 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMips64InstrInfo.td166 def DMULT : Mul64<0x1c, "dmult", IIImul>;
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips3.s8 …dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips4.s26 …dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/mips3/
Dvalid.s78 dmult $s7,$9
/external/llvm/test/MC/Disassembler/Mips/mips3/
Dvalid-mips3-el.txt71 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
/external/llvm/test/MC/Mips/mips5/
Dvalid.s82 dmult $s7,$9
/external/llvm/test/MC/Mips/mips4/
Dvalid.s82 dmult $s7,$9
/external/llvm/test/MC/Mips/mips64/
Dvalid.s89 dmult $s7,$9
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-mips64r5.txt111 0x01 0x7a 0x00 0x1c # CHECK: dmult $11, $26
133 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-mips64r3.txt111 0x01 0x7a 0x00 0x1c # CHECK: dmult $11, $26
133 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9

12