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Searched refs:drotr32 (Results 1 – 25 of 28) sorted by relevance

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/external/valgrind/none/tests/mips64/
Drotate_swap.stdout.exp-mips64r223 drotr32 :: in 0x2000ffffffffffff, out 0xffffffffffff2000, SA 16
24 drotr32 :: in 0xffff0000ffffffff, out 0xffffffffffff, SA 16
25 drotr32 :: in 0x2000ffffffffffff, out 0xffffffffff2000ff, SA 8
26 drotr32 :: in 0x2000ffffffffffff, out 0xfffffffff2000fff, SA 4
27 drotr32 :: in 0x2000ffffffffffff, out 0xfffffffff90007ff, SA 5
28 drotr32 :: in 0x31415927ffffffff, out 0x49ffffffffcc5056, SA 10
29 drotr32 :: in 0x2000ffffffffffff, out 0xfffffffff2000fff, SA 4
30 drotr32 :: in 0x2000ffffffffffff, out 0xffffffff2000ffff, SA 0
31 drotr32 :: in 0xeeeeffffffffffff, out 0xffffffffffffeeee, SA 16
32 drotr32 :: in 0x2000ffffffffffff, out 0x4001fffffffffffe, SA 31
[all …]
Dshift_instructions.stdout.exp-mips64r22049 drotr32 $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
2050 drotr32 $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
2051 drotr32 $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
2052 drotr32 $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
2053 drotr32 $t0, $t1, 0x00 :: rt 0x12bd6aa00000000, rs 0x12bd6aa, imm 0x0000
2054 drotr32 $t2, $t3, 0x1f :: rt 0x257ad54, rs 0x12bd6aa, imm 0x001f
2055 drotr32 $a0, $a1, 0x0f :: rt 0x257ad540000, rs 0x12bd6aa, imm 0x000f
2056 drotr32 $s0, $s1, 0x03 :: rt 0x257ad540000000, rs 0x12bd6aa, imm 0x0003
2057 drotr32 $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
2058 drotr32 $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
/external/llvm/test/MC/Mips/
Dset-mips-directives.s31 drotr32 $1,$14,15
34 drotr32 $1,$14,15
37 drotr32 $1,$14,15
67 # CHECK: drotr32 $1, $14, 15
70 # CHECK: drotr32 $1, $14, 15
73 # CHECK: drotr32 $1, $14, 15
Drotations64.s108 # CHECK-64R: drotr32 $4, $4, 31 # encoding: [0x00,0x24,0x27,0xfe]
116 # CHECK-64R: drotr32 $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfe]
121 # CHECK-64R: drotr32 $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7e]
126 # CHECK-64R: drotr32 $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3e]
144 # CHECK-64R: drotr32 $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfe]
149 # CHECK-64R: drotr32 $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7e]
154 # CHECK-64R: drotr32 $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3e]
200 # CHECK-64R: drotr32 $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3e]
205 # CHECK-64R: drotr32 $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7e]
210 # CHECK-64R: drotr32 $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfe]
[all …]
Dset-arch.s30 drotr32 $1, $14, 15
33 drotr32 $1, $14, 15
36 drotr32 $1, $14, 15
63 # CHECK: drotr32 $1, $14, 15
Dmips64-alu-instructions.s77 # CHECK: drotr32 $9, $6, 20 # encoding: [0x3e,0x4d,0x26,0x00]
102 drotr32 $9, $6, 20
Dset-mips-directives-bad.s33 drotr32 $1,$14,15 # CHECK: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips64/
Dinvalid-mips64r2.s17 …drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
18 …drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips5/
Dinvalid-mips64r2.s16 …drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
17 …drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s98 …drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x…
99 …drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s98 …drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x…
99 …drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s98 …drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x…
99 …drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dmips64shift.ll97 ; CHECK: drotr32 ${{[0-9]+}}, ${{[0-9]+}}, 22
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-mips64r5-el.txt124 0xfe 0x0b 0x21 0x00 # CHECK: drotr32 $1, $1, 15
125 0xfe 0x0b 0x2e 0x00 # CHECK: drotr32 $1, $14, 15
Dvalid-mips64r5.txt53 0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15
57 0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-mips64r3-el.txt124 0xfe 0x0b 0x21 0x00 # CHECK: drotr32 $1, $1, 15
125 0xfe 0x0b 0x2e 0x00 # CHECK: drotr32 $1, $14, 15
Dvalid-mips64r3.txt53 0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15
57 0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15
/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrInfo.td61 class DROTR32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr32", 0b011001000>;
260 class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5,
DMips64InstrInfo.td172 def DROTR32 : StdMMR6Rel, shift_rotate_imm<"drotr32", uimm5, GPR64Opnd,
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-mips64r2-el.txt127 0xfe 0x0b 0x21 0x00 # CHECK: drotr32 $1, $1, 15
128 0xfe 0x0b 0x2e 0x00 # CHECK: drotr32 $1, $14, 15
Dvalid-mips64r2.txt56 0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15
60 0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMips64InstrInfo.td129 def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr,
/external/llvm/test/MC/Mips/micromips64r6/
Dvalid.s301 drotr32 $1, $2, 4 # CHECK: drotr32 $1, $2, 4 # encoding: [0x58,0x22,0x20,0xc8]
Dinvalid.s292 …drotr32 $1, $2, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immedi…
293 …drotr32 $1, $2, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immedi…
/external/llvm/test/MC/Disassembler/Mips/micromips64r6/
Dvalid.txt290 0x58 0x22 0x20 0xc8 # CHECK: drotr32 $1, $2, 4

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