Home
last modified time | relevance | path

Searched refs:dsrl (Results 1 – 25 of 55) sorted by relevance

123

/external/llvm/test/CodeGen/Mips/
Dmips64signextendsesf.ll15 ; CHECK-NOT: dsrl
29 ; CHECK-NOT: dsrl
43 ; CHECK-NOT: dsrl
57 ; CHECK-NOT: dsrl
71 ; CHECK-NOT: dsrl
85 ; CHECK-NOT: dsrl
97 ; CHECK-NOT: dsrl
109 ; CHECK-NOT: dsrl
123 ; CHECK-NOT: dsrl
140 ; CHECK-NOT: dsrl
[all …]
Docteon.ll38 ; MIPS64: dsrl $2, $[[T2]], 32
54 ; MIPS64: dsrl $2, $[[T3]], 32
69 ; MIPS64: dsrl $2, $[[T2]], 32
85 ; MIPS64: dsrl $2, $[[T3]], 32
Dmips64shift.ll41 ; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
62 ; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
Dmips64sinttofpsf.ll13 ; CHECK-NOT: dsrl
Dmips64ext.ll8 ; CHECK: dsrl ${{[0-9]+}}, $[[R1]], 32
Dfcopysign-f32-f64.ll19 ; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
/external/llvm/test/MC/Mips/
Drotations64.s110 # CHECK-64: dsrl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3a]
129 # CHECK-64: dsrl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfa]
134 # CHECK-64: dsrl $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7a]
138 # CHECK-64: dsrl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3a]
157 # CHECK-64: dsrl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfa]
162 # CHECK-64: dsrl $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7a]
179 # CHECK-64: dsrl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x7a]
184 # CHECK-64: dsrl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3a]
187 # CHECK-64: dsrl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x7a]
192 # CHECK-64: dsrl $1, $5, 31 # encoding: [0x00,0x05,0x0f,0xfa]
[all …]
Delf-gprel-32-64.s49 dsrl $3, $3, 32
Dmips64shift.ll23 ; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
Ddo_switch3.s41 dsrl $2, $3, 32
/external/valgrind/none/tests/mips64/
Dshift_instructions.stdout.exp-mips649217 dsrl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
9218 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
9219 dsrl $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
9220 dsrl $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
9221 dsrl $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
9222 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
9223 dsrl $a0, $a1, 0x0f :: rt 0x257, rs 0x12bd6aa, imm 0x000f
9224 dsrl $s0, $s1, 0x03 :: rt 0x257ad5, rs 0x12bd6aa, imm 0x0003
9225 dsrl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
9226 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
Dshift_instructions.stdout.exp-mips64r213825 dsrl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
13826 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
13827 dsrl $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
13828 dsrl $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
13829 dsrl $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
13830 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
13831 dsrl $a0, $a1, 0x0f :: rt 0x257, rs 0x12bd6aa, imm 0x000f
13832 dsrl $s0, $s1, 0x03 :: rt 0x257ad5, rs 0x12bd6aa, imm 0x0003
13833 dsrl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
13834 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
/external/llvm/test/MC/Mips/mips3/
Dvalid.s95 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
96 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
97 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s40 …dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
41 …dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
42 …dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
Dinvalid-mips4.s38 …dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
39 …dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
40 …dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips5.s37 …dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
38 …dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
39 …dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Mips/mips5/
Dvalid.s99 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
100 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
101 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips4/
Dvalid.s99 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
100 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
101 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips64/
Dvalid.s106 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
107 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
108 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s115 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
116 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
117 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s115 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
116 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
117 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s115 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
116 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
117 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dshl.ll180 ; M3: dsrl $[[T5:[0-9]+]], $5, 1
193 ; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1
205 ; 64R6: dsrl $[[T1:[0-9]+]], $5, 1
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips3.s44 …dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
45 …dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
46 …dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/python/cpython2/Modules/_ctypes/libffi/src/mips/
Dffitarget.h159 # define SRL dsrl

123