| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | lshr.ll | 123 ; GP64: dsrlv $2, $4, $5
159 ; M3: dsrlv $[[T1:[0-9]+]], $4, $7
163 ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
176 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
182 ; GP64-NOT-R6: dsrlv $2, $4, $7
188 ; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7
197 ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7
|
| D | ashr.ll | 172 ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
185 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
206 ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7
|
| D | shl.ll | 182 ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
196 ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
208 ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
|
| /external/llvm/test/MC/Mips/ |
| D | rotations64.s | 91 # CHECK-64: dsrlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x16]
98 # CHECK-64: dsrlv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x16]
169 # CHECK-64: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
175 # CHECK-64: dsrlv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x16]
|
| /external/valgrind/none/tests/mips64/ |
| D | shift_instructions.stdout.exp-mips64 | 13313 dsrlv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4
13314 dsrlv $s0, $s1, $s2 :: rd 0x0, rs 0x12bd6aa, rt 0xa2a6ec661ba84121
13315 dsrlv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03
13316 dsrlv $s0, $s1, $s2 :: rd 0xfd0, rs 0x7e876382d2ab13, rt 0x614d9b445f12236b
13317 dsrlv $t0, $t1, $t2 :: rd 0x2, rs 0x9823b6e, rt 0xffffffffb8757bda
13318 dsrlv $s0, $s1, $s2 :: rd 0x4bb, rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75
13319 dsrlv $t0, $t1, $t2 :: rd 0x0, rs 0xd4326d9, rt 0xffffffffbcb4666d
13320 dsrlv $s0, $s1, $s2 :: rd 0x2ddd1b5, rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666
13321 dsrlv $t0, $t1, $t2 :: rd 0x0, rs 0x130476dc, rt 0xffffffffa2f33668
13322 dsrlv $s0, $s1, $s2 :: rd 0x856181450c, rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17
[all …]
|
| D | shift_instructions.stdout.exp-mips64r2 | 17921 dsrlv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4
17922 dsrlv $s0, $s1, $s2 :: rd 0x0, rs 0x12bd6aa, rt 0xa2a6ec661ba84121
17923 dsrlv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03
17924 dsrlv $s0, $s1, $s2 :: rd 0xfd0, rs 0x7e876382d2ab13, rt 0x614d9b445f12236b
17925 dsrlv $t0, $t1, $t2 :: rd 0x2, rs 0x9823b6e, rt 0xffffffffb8757bda
17926 dsrlv $s0, $s1, $s2 :: rd 0x4bb, rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75
17927 dsrlv $t0, $t1, $t2 :: rd 0x0, rs 0xd4326d9, rt 0xffffffffbcb4666d
17928 dsrlv $s0, $s1, $s2 :: rd 0x2ddd1b5, rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666
17929 dsrlv $t0, $t1, $t2 :: rd 0x0, rs 0x130476dc, rt 0xffffffffa2f33668
17930 dsrlv $s0, $s1, $s2 :: rd 0x856181450c, rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17
[all …]
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 97 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
100 …dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | mips64shift.ll | 19 ; CHECK: dsrlv
|
| /external/llvm/test/CodeGen/Mips/ |
| D | mips64shift.ll | 20 ; ALL: dsrlv
|
| /external/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 101 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
104 …dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
|
| /external/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 101 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
104 …dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
|
| /external/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 108 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
111 …dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 117 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
120 …dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 117 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
120 …dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| D | valid.s | 117 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
120 …dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64-el.txt | 105 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
108 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
236 0x16 0xe0 0xea 0x02 # CHECK: dsrlv $gp, $10, $23
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-mips64r2-el.txt | 111 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
114 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
257 0x16 0xe0 0xea 0x02 # CHECK: dsrlv $gp, $10, $23
|
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| D | valid-mips3-el.txt | 87 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
90 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
|
| D | valid-mips3.txt | 82 0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
83 0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| D | valid-mips4-el.txt | 91 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
94 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
|
| D | valid-mips4.txt | 84 0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
85 0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| D | valid-mips64r5-el.txt | 108 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
111 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| D | valid-mips64r3-el.txt | 108 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
111 0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips3.s | 45 …dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 69 class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>;
266 class DSRLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrlv", II_DSRLV, srl>;
|