Searched refs:elt2 (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | sign_extend.ll | 88 %elt2 = extractelement <4 x i32> %ext, i32 2
92 store volatile i32 %elt2, i32 addrspace(1)* %out
114 %elt2 = extractelement <4 x i32> %ext, i32 2
118 store volatile i32 %elt2, i32 addrspace(1)* %out
135 %elt2 = extractelement <4 x i32> %ext, i32 2
139 store volatile i32 %elt2, i32 addrspace(1)* %out
158 %elt2 = extractelement <4 x i32> %ext, i32 2
162 store volatile i32 %elt2, i32 addrspace(1)* %out
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| D | extract-vector-elt-build-vector-combine.ll | 22 %elt2 = load volatile i32, i32 addrspace(1)* %in
27 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
64 %elt2 = load volatile i32, i32 addrspace(1)* %in
69 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
108 %elt2 = load volatile i32, i32 addrspace(1)* %in
113 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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| D | extractelt-to-trunc.ll | 63 %elt2 = extractelement <4 x i32> %vec, i32 2
64 store i32 %elt2, i32 addrspace(1)* %out
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| D | ds_read2_superreg.ll | 52 %elt2 = extractelement <4 x float> %val0, i32 2
55 %add0 = fadd float %elt0, %elt2
77 %elt2 = extractelement <3 x float> %val0, i32 2
79 %add0 = fadd float %elt0, %elt2
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| D | salu-to-valu.ll | 327 %elt2 = extractelement <8 x i32> %tmp3, i32 2
335 %add1 = add i32 %add0, %elt2
399 %elt2 = extractelement <16 x i32> %tmp3, i32 2
415 %add1 = add i32 %add0, %elt2
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | 2009-08-19-LoadNarrowingMiscompile.ll | 9 %sroa.store.elt2 = lshr i96 %srcval1, 64
10 %tmp = trunc i96 %sroa.store.elt2 to i64
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| /external/llvm/test/CodeGen/X86/ |
| D | 2009-08-19-LoadNarrowingMiscompile.ll | 9 %sroa.store.elt2 = lshr i96 %srcval1, 64
10 %tmp = trunc i96 %sroa.store.elt2 to i64
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | vec-perm-12.ll | 35 %elt2 = extractelement <4 x i32> %x, i32 1
39 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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| D | vec-combine-02.ll | 393 %elt2 = extractelement <4 x float> %pack, i32 2
395 %add0 = fadd float %elt0, %elt2
427 %elt2 = extractelement <4 x i32> %pack, i32 2
429 %add0 = add i32 %elt0, %elt2
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| /external/swiftshader/third_party/subzero/tests_lit/assembler/x86/ |
| D | opcode_register_encodings.ll | 173 define internal <4 x i32> @test_pinsrd(<4 x i32> %vec, i32 %elt1, i32 %elt2,
176 %elt12 = add i32 %elt1, %elt2
192 %elt2 = trunc i32 %elt2_w to i8
195 %elt12 = add i8 %elt1, %elt2
211 %elt2 = trunc i32 %elt2_w to i16
214 %elt12 = add i16 %elt1, %elt2
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| /external/webrtc/webrtc/libjingle/xmllite/ |
| D | xmlelement_unittest.cc | 33 XmlElement elt2(QName("google:test", "first"), true); in TEST() local
34 EXPECT_EQ("<first xmlns=\"google:test\"/>", elt2.Str()); in TEST()
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| /external/python/cpython2/Tools/compiler/ |
| D | astgen.py | 250 for elt2 in flatten(elt):
251 l.append(elt2)
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| /external/llvm/test/Transforms/InstCombine/ |
| D | insert-extract-shuffle.ll | 16 %elt2 = extractelement <8 x i16> %in2, i32 0
21 %vec.2 = insertelement <4 x i16> %vec.1, i16 %elt2, i32 2
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| /external/python/cpython2/Lib/compiler/ |
| D | ast.py | 12 for elt2 in flatten(elt):
13 l.append(elt2)
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