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/external/webrtc/webrtc/modules/audio_processing/aec/
Daec_rdft_mips.c272 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cft1st_128_mips() local
511 [f8] "=&f" (f8), [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), in cft1st_128_mips()
521 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cftmdl_128_mips() local
628 f10 = rdft_w[3]; in cftmdl_128_mips()
713 : [a] "r" (a), [f9] "f" (f9), [f10] "f" (f10), [f11] "f" (f11), in cftmdl_128_mips()
800 : [a] "r" (a), [f9] "f" (f9), [f10] "f" (f10), [f11] "f" (f11), in cftmdl_128_mips()
929 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftfsub_128_mips() local
1041 [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), [f12] "=&f" (f12), in rftfsub_128_mips()
1056 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftbsub_128_mips() local
1171 [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), [f12] "=&f" (f12), in rftbsub_128_mips()
Daec_core_mips.c345 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13; in WebRtcAec_FilterFar_mips() local
432 [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), in WebRtcAec_FilterFar_mips()
465 float f0, f1, f2, f3, f4, f5, f6 ,f7, f8, f9, f10, f11, f12; in WebRtcAec_FilterAdaptation_mips() local
530 [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), in WebRtcAec_FilterAdaptation_mips()
/external/llvm/test/CodeGen/SystemZ/
Dframe-04.ll16 ; CHECK: std %f10, 200(%r15)
24 ; CHECK: .cfi_offset %f10, -184
33 ; CHECK: ld %f10, 200(%r15)
76 ; CHECK: std %f10, 184(%r15)
82 ; CHECK: .cfi_offset %f10, -184
91 ; CHECK: ld %f10, 184(%r15)
122 ; numerical order so the pair should be %f8+%f10.
128 ; CHECK: std %f10, 160(%r15)
130 ; CHECK: .cfi_offset %f10, -176
139 ; CHECK: ld %f10, 160(%r15)
[all …]
Dframe-07.ll17 ; CHECK-NOFP: stdy %f10, 4104(%r15)
25 ; CHECK-NOFP: .cfi_offset %f10, -184
34 ; CHECK-NOFP: ldy %f10, 4104(%r15)
51 ; CHECK-FP: stdy %f10, 4104(%r11)
60 ; CHECK-FP: ldy %f10, 4104(%r11)
138 ; CHECK-NOFP: std %f10, 8({{%r[1-5]}},%r15)
146 ; CHECK-NOFP: .cfi_offset %f10, -184
155 ; CHECK-NOFP: ld %f10, 8({{%r[1-5]}},%r15)
171 ; CHECK-FP: std %f10, 8({{%r[1-5]}},%r11)
179 ; CHECK-FP: .cfi_offset %f10, -184
[all …]
Dframe-03.ll17 ; CHECK: std %f10, 200(%r15)
25 ; CHECK: .cfi_offset %f10, -184
34 ; CHECK: ld %f10, 200(%r15)
101 ; CHECK: std %f10, 192(%r15)
108 ; CHECK: .cfi_offset %f10, -184
117 ; CHECK: ld %f10, 192(%r15)
180 ; CHECK-NOT: %f10
227 ; CHECK-NOT: %f10
Dframe-02.ll15 ; CHECK: std %f10, 200(%r15)
23 ; CHECK: .cfi_offset %f10, -184
32 ; CHECK: ld %f10, 200(%r15)
99 ; CHECK: std %f10, 192(%r15)
106 ; CHECK: .cfi_offset %f10, -184
115 ; CHECK: ld %f10, 192(%r15)
178 ; CHECK-NOT: %f10
225 ; CHECK-NOT: %f10
Dframe-17.ll13 ; CHECK: std %f10, 208(%r15)
26 ; CHECK: ld %f10, 208(%r15)
77 ; CHECK: std %f10, 208(%r15)
87 ; CHECK: ld %f10, 208(%r15)
138 ; CHECK: std %f10, 216(%r15)
150 ; CHECK: ld %f10, 216(%r15)
/external/mesa3d/src/mesa/sparc/
Dnorm.S67 fmuls %f2, M2, %f10 ! FGM Group f5 available
72 fadds %f3, %f10, %f3 ! FGA Group f10 available
81 fmuls %f7, %f7, %f10 ! FGM Group f7 available
83 fadds %f6, %f10, %f6 ! FGA Group 4cyc stall f6,f10 available
132 fmuls %f2, M2, %f10 ! FGM Group f5 available
137 fadds %f3, %f10, %f3 ! FGA Group f10 available
208 fmuls %f7, %f7, %f10 ! FGM Group f7 available
210 fadds %f6, %f10, %f6 ! FGA Group 4cyc stall f6,f10 available
365 fmuls %f2, M2, %f10 ! FGM Group f5 available
370 fadds %f3, %f10, %f3 ! FGA Group f10 available
[all …]
Dxform.S89 fmuls %f8, M1, %f10 ! FGM Group f2 available
100 fadds %f10, M13, %f10 ! FGA Group f10 available
101 st %f10, [%g2 + 0x14] ! LSU
200 fmuls %f8, M1, %f10 ! FGM Group
207 fadds %f10, M13, %f12 ! FGA Group f10 available
545 fmuls %f8, M0, %f10 ! FGM Group f2 available
551 fadds %f10, M12, %f10 ! FGA Group f2, f10 available
557 fadds %f10, %f12, %f10 ! FGA Group f10 available
558 st %f10, [%g2 + 0x10] ! LSU
667 ld [%g1 + 0x04], %f10 ! LSU Group
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/testsuite/libffi.call/
Dmany.c14 …loat f3, float f4, float f5, float f6, float f7, float f8, float f9, float f10, float f11, float f… in many() argument
19 (double) f6, (double) f7, (double) f8, (double) f9, (double) f10, in many()
23 return f1+f2+f3+f4+f5+f6+f7+f8+f9+f10+f11+f12+f13; in many()
/external/llvm/test/MC/SystemZ/
Dregs-good.s62 #CHECK: ler %f10, %f11 # encoding: [0x38,0xab]
71 ler %f10,%f11
80 #CHECK: ldr %f10, %f11 # encoding: [0x28,0xab]
89 ldr %f10,%f11
129 #CHECK: .cfi_offset %f10, 208
163 .cfi_offset %f10,208
/external/libmojo/mojo/public/js/
Dstruct_unittests.js125 f10: new Map([[-100.5, -50000], [0, 50000000]]), // map<double, double> property
139 expect(decodedStruct.f10).toEqual(mapFieldsStruct.f10);
166 f10: new Map([["a", [1234, 5678]]]), property
181 expect(decodedStruct.f10).toEqual(mapFieldsStruct.f10);
211 expect(decodedStruct.f10).toEqual(testStructs.IntegerNumberValues.V10);
236 expect(decodedStruct.f10).toEqual(testStructs.UnsignedNumberValues.V10);
/external/clang/test/Sema/
Dwarn-unused-function.c37 static void f10(void); // expected-warning{{unused}}
38 static void f10(void);
/external/valgrind/none/tests/mips32/
DMoveIns.c284 TESTINSNMOVE("mfc1 $s1, $f10", 40, f10, s1); in main()
313 TESTINSNMOVEt("mtc1 $s1, $f10", 40, f10, s1); in main()
338 TESTINSNMOVEd("mfhc1 $a0, $f10", 40, f10, a0); in main()
356 TESTINSNMOVEtd("mthc1 $a1, $f10", 20, 40, f10, a1); in main()
380 TESTINSNMOVE1s("mov.s $f9, $f10", 40, f9, f10); in main()
381 TESTINSNMOVE1s("mov.s $f10, $f11", 44, f10, f11); in main()
408 TESTINSNMOVE1d("mov.d $f8, $f10", 0, f8, f10); in main()
409 TESTINSNMOVE1d("mov.d $f8, $f10", 8, f8, f10); in main()
410 TESTINSNMOVE1d("mov.d $f10, $f12", 16, f10, f12); in main()
411 TESTINSNMOVE1d("mov.d $f10, $f12", 24, f10, f12); in main()
/external/clang/test/CodeGenCXX/
Dmangle-variadic-templates.cpp74 template<typename ...T> void f10(ArrayOfN<T...> &) {} in f10() function
77 template void f10<int, float>(int (&)[2]);
/external/clang/test/CXX/except/except.spec/
Dp5-virtual.cpp38 virtual void f10() noexcept(false);
74 virtual void f10() noexcept(false);
/external/python/cpython2/Modules/_ctypes/libffi/src/ia64/
Dunix.S67 ldf.fill f10 = [in0], 32
210 (p7) stfs [in1] = f10, 8
234 (p7) stfd [in1] = f10, 16
258 (p7) stfe [in1] = f10, 32
312 stf.spill [r16] = f10, 32
439 (p7) ldfs f10 = [r16], 8
467 (p7) ldfd f10 = [r16], 16
495 (p7) ldfe f10 = [r16], 32
/external/llvm/test/MC/Mips/
Dmips-reginfo-fp32.s29 # ceil.w.s - Reads $f8 and writes to $f10.
30 ceil.w.s $f10, $f8
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dfpconv.ll94 define double @f10(i32 %a) {
95 ;CHECK-VFP: f10:
97 ;CHECK: f10:
/external/llvm/test/CodeGen/ARM/
Dfpconv.ll94 define double @f10(i32 %a) {
95 ;CHECK-VFP-LABEL: f10:
97 ;CHECK-LABEL: f10:
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-tst.ll43 define i1 @f10(i32 %a) {
48 ; CHECK-LABEL: f10:
/external/llvm/test/CodeGen/PowerPC/
Dppc64-fastcc.ll7 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
15 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
23 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
31 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
39 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
47 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
55 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
63 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
71 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
79 … %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i6…
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-xfail-mips64r5.txt28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
33 0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
54 0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-xfail-mips64r3.txt28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
33 0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
54 0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-xfail-mips64r2.txt28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
33 0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
54 0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20

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