| /external/linux-kselftest/tools/testing/selftests/powerpc/include/ |
| D | fpu_asm.h | 17 stfd f29,(stack_size + STACK_FRAME_MIN_SIZE - 16)(%r1); \
37 lfd f29,(stack_size + STACK_FRAME_MIN_SIZE - 16)(%r1); \
74 lfd f29,120(r3)
|
| /external/llvm/test/MC/Sparc/ |
| D | sparc-fp-instructions.s | 141 ! CHECK: ld [%l0], %f29 ! encoding: [0xfb,0x04,0x00,0x00]
143 ld [%l0], %f29
146 ! CHECK: st %f29, [%l0] ! encoding: [0xfb,0x24,0x00,0x00]
148 st %f29, [%l0]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | vsx-spill.ll | 10 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() n…
31 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() n…
51 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0…
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | invalid-mips5-wrong-error.s | 24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| D | valid.s | 9 add.d $f1,$f7,$f29
27 c.ngl.d $f29,$f29
40 div.d $f29,$f20,$f27
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | invalid-mips5-wrong-error.s | 24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| D | valid.s | 11 add.d $f1,$f7,$f29
40 c.ngl.d $f29,$f29
54 cvt.l.s $f11,$f29
73 div.d $f29,$f20,$f27
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips5-wrong-error.s | 24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| D | valid.s | 11 add.d $f1,$f7,$f29
39 c.ngl.d $f29,$f29
54 div.d $f29,$f20,$f27
|
| /external/llvm/test/MC/Mips/mips4/ |
| D | invalid-mips5-wrong-error.s | 24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
58 cvt.l.s $f11,$f29
77 div.d $f29,$f20,$f27
168 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips5-wrong-error.s | 27 … c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
39 … msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
45 … plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| D | invalid-mips1.s | 14 …c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
57 cvt.l.s $f11,$f29
66 div.d $f29,$f20,$f27
127 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
57 cvt.l.s $f11,$f29
66 div.d $f29,$f20,$f27
128 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
57 cvt.l.s $f11,$f29
66 div.d $f29,$f20,$f27
127 movz.d $f12,$f29,$9
|
| /external/llvm/test/CodeGen/Mips/ |
| D | no-odd-spreg-msa.ll | 26 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
60 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
90 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
118 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
|
| D | no-odd-spreg.ll | 24 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
48 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | callee-saved-float.ll | 28 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
70 ; O32-INV-NOT: sdc1 $f29,
89 ; N32-INV-NOT: sdc1 $f29,
102 ; N64-DAG: sdc1 [[F29:\$f29]], [[OFF29:[0-9]+]]($sp)
|
| /external/llvm/test/MC/Mips/mips32/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
62 div.d $f29,$f20,$f27
112 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/ARM/ |
| D | symbol-variants.s | 95 ldr r3, =f29(GOT_PREL)
97 @ CHECK: 78 R_ARM_GOT_PREL f29
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips1.s | 11 …c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
58 cvt.l.s $f11,$f29
77 div.d $f29,$f20,$f27
169 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
60 cvt.l.s $f11,$f29
82 div.d $f29,$f20,$f27
181 movz.d $f12,$f29,$9
|
| /external/libjpeg-turbo/simd/ |
| D | jsimd_mips_dspr2_asm.h | 88 #define f29 $f29 macro
|