| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vcvtxd_f32_f64.ll | 3 define float @fcvtxn(double %a) {
4 ; CHECK-LABEL: fcvtxn:
5 ; CHECK: fcvtxn s0, d0
7 %vcvtxd.i = tail call float @llvm.aarch64.sisd.fcvtxn(double %a) nounwind
11 declare float @llvm.aarch64.sisd.fcvtxn(double) nounwind readnone
|
| D | arm64-vcvt_f.ll | 41 %vcvtx1.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
42 ; CHECK: fcvtxn
49 %vcvtx2.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
63 declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
|
| D | arm64-vcvt.ll | 526 ;CHECK: fcvtxn v0.2s, v0.2d
528 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
537 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
542 declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-cvt.s | 82 fcvtxn s22, d13
|
| D | neon-simd-misc.s | 438 fcvtxn v4.2s, v0.2d
|
| D | neon-diagnostics.s | 5820 fcvtxn v6.4s, v8.2d
7166 fcvtxn s0, s1
|
| D | arm64-advsimd.s | 866 fcvtxn v6.2s, v9.2d
873 ; CHECK: fcvtxn v6.2s, v9.2d ; encoding: [0x26,0x69,0x61,0x2e]
|
| /external/vixl/test/aarch64/ |
| D | test-simulator-aarch64.cc | 4344 DEFINE_TEST_NEON_2DIFF_FP_NARROW_2S(fcvtxn, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4391 CALL_TEST_NEON_HELPER_2DIFF(fcvtxn, S, D, kInputDoubleConversions); in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
|
| D | test-trace-aarch64.cc | 494 __ fcvtxn(s12, d12); in GenerateTestSequenceFP() local
2595 __ fcvtxn(v29.V2S(), v11.V2D()); in GenerateTestSequenceNEONFP() local
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 3122 fcvtxn(vf_fcvtn, rd, rn); in VisitNEON2RegMisc()
4556 fcvtxn(kFormatS, rd, rn); in VisitNEONScalar2RegMisc()
|
| D | assembler-aarch64.h | 1438 void fcvtxn(const VRegister& vd, const VRegister& vn);
|
| D | simulator-aarch64.h | 2861 LogicVRegister fcvtxn(VectorFormat vform,
|
| D | macro-assembler-aarch64.h | 1215 fcvtxn(vd, vn); in Fcvtxn()
|
| D | logic-aarch64.cc | 4575 LogicVRegister Simulator::fcvtxn(VectorFormat vform, in fcvtxn() function in vixl::aarch64::Simulator
|
| D | assembler-aarch64.cc | 2329 void Assembler::fcvtxn(const VRegister& vd, const VRegister& vn) { in fcvtxn() function in vixl::aarch64::Assembler
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 417 0x~~~~~~~~~~~~~~~~ 7e61698c fcvtxn s12, d12
2243 0x~~~~~~~~~~~~~~~~ 2e61697d fcvtxn v29.2s, v11.2d
|
| D | log-disasm-colour | 417 0x~~~~~~~~~~~~~~~~ 7e61698c fcvtxn s12, d12
2243 0x~~~~~~~~~~~~~~~~ 2e61697d fcvtxn v29.2s, v11.2d
|
| D | log-all | 969 0x~~~~~~~~~~~~~~~~ 7e61698c fcvtxn s12, d12
5789 0x~~~~~~~~~~~~~~~~ 2e61697d fcvtxn v29.2s, v11.2d
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2032 void fcvtxn(const VRegister& vd, const VRegister& vn)
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 563 # CHECK: fcvtxn v0.2s, v0.2d
|
| D | neon-instructions.txt | 2535 # CHECK: fcvtxn s22, d13
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2817 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
3358 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 26838 fcvtxn s10, d21 6703e8d6cbffa3e96e2088fe0c404ef3 acdc6e6f4bf5a9501d87ee7e4d861e1c 0000000000000…
26839 fcvtxn v10.2s, v21.2d d2dcb2a585e4bade8d3a11f81ddbd8a4 3b2152911c72e8d11d9fc6b5613bb6b1 000000…
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 209 aarch64_neon_fcvtxn, // llvm.aarch64.neon.fcvtxn
346 aarch64_sisd_fcvtxn, // llvm.aarch64.sisd.fcvtxn
6267 "llvm.aarch64.neon.fcvtxn",
6404 "llvm.aarch64.sisd.fcvtxn",
14207 1, // llvm.aarch64.neon.fcvtxn
14344 1, // llvm.aarch64.sisd.fcvtxn
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 201 aarch64_neon_fcvtxn, // llvm.aarch64.neon.fcvtxn
337 aarch64_sisd_fcvtxn, // llvm.aarch64.sisd.fcvtxn
6225 "llvm.aarch64.neon.fcvtxn",
6361 "llvm.aarch64.sisd.fcvtxn",
14110 1, // llvm.aarch64.neon.fcvtxn
14246 1, // llvm.aarch64.sisd.fcvtxn
|