/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | MachineInstr.h | 338 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; 345 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; 353 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; 375 int findRegisterDefOperandIdx(unsigned Reg, 383 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
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/external/llvm/include/llvm/CodeGen/ |
D | MachineInstr.h | 907 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; 914 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; 922 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; 956 int findRegisterDefOperandIdx(unsigned Reg, 964 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
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/external/llvm/lib/CodeGen/ |
D | MachineCombiner.cpp | 156 DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()), in getDepth() 163 DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()), in getDepth() 205 NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO, in getLatency()
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D | AggressiveAntiDepBreaker.cpp | 687 int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI); in FindSuitableFreeRegisters()
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D | TwoAddressInstructionPass.cpp | 1326 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in tryInstructionTransform()
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D | MachineInstr.cpp | 1340 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, in findRegisterDefOperandIdx() function in MachineInstr
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D | RegisterCoalescer.cpp | 671 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in removeCopyByCommutingDef()
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/external/llvm/lib/Target/AMDGPU/ |
D | R600EmitClauseMarkers.cpp | 218 if (UseI != Def && UseI->findRegisterDefOperandIdx(MOI->getReg()) != -1) in canClauseLocalKillFitInClause()
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D | R600InstrInfo.cpp | 231 return MI.findRegisterDefOperandIdx(AMDGPU::AR_X) != -1; in definesAddressRegister()
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D | SIInstrInfo.cpp | 2939 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC) != -1) in addSCCDefUsersToVALUWorklist()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | ScheduleDAGInstrs.cpp | 600 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg); in ComputeOperandLatency() 611 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI); in ComputeOperandLatency()
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D | LiveIntervalAnalysis.cpp | 279 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1; in isPartialRedef() 537 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_); in handlePhysicalRegisterDef()
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D | TwoAddressInstructionPass.cpp | 978 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in TryInstructionTransform()
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D | MachineInstr.cpp | 946 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, in findRegisterDefOperandIdx() function in MachineInstr
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D | RegisterCoalescer.cpp | 659 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in RemoveCopyByCommutingDef()
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZElimCompare.cpp | 300 int CCDef = MI.findRegisterDefOperandIdx(SystemZ::CC, false, true, TRI); in adjustCCMasksForInstr()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.cpp | 316 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel() 343 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel() 889 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true); in optimizeCompareInstr() 2928 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true); in getMaddPatterns() 3944 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) in optimizeCondBranch()
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/external/llvm/lib/Target/ARM/ |
D | ARMBaseInstrInfo.cpp | 1333 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD); in expandPostRAPseudo() 3451 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); in getBundledDefMI()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMBaseInstrInfo.cpp | 1037 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); in expandPostRAPseudo()
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