| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-fminv.ll | 31 %max = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %in)
37 ; CHECK: fmaxv s0, v0.4s
38 %max = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %in)
45 %max = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %in)
49 declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)
50 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
51 declare double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double>)
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| D | arm64-neon-across.ll | 9 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
431 ; CHECK: fmaxv s{{[0-9]+}}, {{v[0-9]+}}.4s
433 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %a)
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| D | arm64-neon-copy.ll | 1069 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %a)
1081 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %a)
1088 declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-across.s | 95 fmaxv h0, v1.4h
99 fmaxv h0, v1.8h
103 fmaxv s0, v1.4s
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| D | fullfp16-neon-neg.s | 76 fmaxv h0, v1.8h
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| D | neon-diagnostics.s | 3819 fmaxv b0, v1.16b
3837 fmaxv h0, v1.8h
3855 fmaxv d0, v1.2d define
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2083 void fmaxv(const VRegister& vd, const VRegister& vn);
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| D | simulator-aarch64.h | 2894 LogicVRegister fmaxv(VectorFormat vform,
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| D | macro-assembler-aarch64.h | 2281 V(fmaxv, Fmaxv) \
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| D | simulator-aarch64.cc | 3693 fmaxv(vf, rd, rn); in VisitNEONAcrossLanes()
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| D | logic-aarch64.cc | 4323 LogicVRegister Simulator::fmaxv(VectorFormat vform, in fmaxv() function in vixl::aarch64::Simulator
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| D | assembler-aarch64.cc | 3479 V(fmaxv, NEON_FMAXV, vd.Is1S()) \
|
| /external/vixl/test/aarch64/ |
| D | test-simulator-aarch64.cc | 4413 DEFINE_TEST_NEON_ACROSS_FP(fmaxv, Basic)
|
| D | test-trace-aarch64.cc | 2629 __ fmaxv(s31, v29.V4S()); in GenerateTestSequenceNEONFP() local
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2147 void fmaxv(const VRegister& vd,
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| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 2277 0x~~~~~~~~~~~~~~~~ 6e30fbbf fmaxv s31, v29.4s
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| D | log-disasm-colour | 2277 0x~~~~~~~~~~~~~~~~ 6e30fbbf fmaxv s31, v29.4s
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| D | log-all | 5857 0x~~~~~~~~~~~~~~~~ 6e30fbbf fmaxv s31, v29.4s
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4133 defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 26537 fmaxv s2, v23.4s 0a310924d3812f3aa00d9cfc92a069a4 2fccd9b9c15d84b5a26d3d670101e66b 000000000000…
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| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 217 aarch64_neon_fmaxv, // llvm.aarch64.neon.fmaxv
6275 "llvm.aarch64.neon.fmaxv",
14215 1, // llvm.aarch64.neon.fmaxv
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 209 aarch64_neon_fmaxv, // llvm.aarch64.neon.fmaxv
6233 "llvm.aarch64.neon.fmaxv",
14118 1, // llvm.aarch64.neon.fmaxv
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 217 aarch64_neon_fmaxv, // llvm.aarch64.neon.fmaxv
6275 "llvm.aarch64.neon.fmaxv",
14215 1, // llvm.aarch64.neon.fmaxv
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 217 aarch64_neon_fmaxv, // llvm.aarch64.neon.fmaxv
6275 "llvm.aarch64.neon.fmaxv",
14215 1, // llvm.aarch64.neon.fmaxv
|