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Searched refs:fpusw (Results 1 – 6 of 6) sorted by relevance

/external/valgrind/none/tests/x86/
Dx87trigOOR.c15 typedef struct { Double arg; Double st0; Double st1; UShort fpusw; } Res; member
30 assert(my_offsetof(Res,fpusw) == 24); in do_fsin()
52 assert(my_offsetof(Res,fpusw) == 24); in do_fcos()
74 assert(my_offsetof(Res,fpusw) == 24); in do_fsincos()
96 assert(my_offsetof(Res,fpusw) == 24); in do_fptan()
119 r.fpusw &= (1 << SHIFT_C2); in try()
121 name, r.arg, r.st0, r.st1, (UInt)r.fpusw); in try()
Dinsn_fpu.def61 fcoms st0.ps[1234.5678] : m32.ps[1234.5676] => st0.ps[1234.5678] fpusw[0x4700,0x0000]
62 fcoms st0.ps[1234.5678] : m32.ps[1234.5679] => st0.ps[1234.5678] fpusw[0x4700,0x0100]
63 fcoms st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[1234.5678] fpusw[0x4700,0x4000]
64 fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[1234567.7654321] fpusw[0x4700,0x0…
65 fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654322] => st0.pd[1234567.7654321] fpusw[0x4700,0x0…
66 fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654321] => st0.pd[1234567.7654321] fpusw[0x4700,0x4…
67 fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5676] => st0.ps[8765.4321] fpusw[0x4700,0x…
68 fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5679] => st0.ps[8765.4321] fpusw[0x4700,0x…
69 fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[8765.4321] fpusw[0x4700,0x…
70 …] st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[7654321.1234567] fpusw[0x4700,0x0000]
[all …]
Dgen_insn_test.pl21 fpusw => "reg16_t"
/external/valgrind/none/tests/amd64/
Dx87trigOOR.c15 typedef struct { Double arg; Double st0; Double st1; UShort fpusw; } Res; member
30 assert(my_offsetof(Res,fpusw) == 24); in do_fsin()
52 assert(my_offsetof(Res,fpusw) == 24); in do_fcos()
74 assert(my_offsetof(Res,fpusw) == 24); in do_fsincos()
96 assert(my_offsetof(Res,fpusw) == 24); in do_fptan()
119 r.fpusw &= (1 << SHIFT_C2); in try()
121 name, r.arg, r.st0, r.st1, (UInt)r.fpusw); in try()
Dinsn_fpu.def61 fcoms st0.ps[1234.5678] : m32.ps[1234.5676] => st0.ps[1234.5678] fpusw[0x4700,0x0000]
62 fcoms st0.ps[1234.5678] : m32.ps[1234.5679] => st0.ps[1234.5678] fpusw[0x4700,0x0100]
63 fcoms st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[1234.5678] fpusw[0x4700,0x4000]
64 fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[1234567.7654321] fpusw[0x4700,0x0…
65 fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654322] => st0.pd[1234567.7654321] fpusw[0x4700,0x0…
66 fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654321] => st0.pd[1234567.7654321] fpusw[0x4700,0x4…
67 fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5676] => st0.ps[8765.4321] fpusw[0x4700,0x…
68 fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5679] => st0.ps[8765.4321] fpusw[0x4700,0x…
69 fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[8765.4321] fpusw[0x4700,0x…
70 …] st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[7654321.1234567] fpusw[0x4700,0x0000]
[all …]
Dgen_insn_test.pl22 fpusw => "reg16_t"