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/external/llvm/test/CodeGen/NVPTX/
Drefl1.ll15 declare float @llvm.nvvm.sin.approx.ftz.f(float) #1
18 declare float @llvm.nvvm.cos.approx.ftz.f(float) #1
21 declare float @llvm.nvvm.div.approx.ftz.f(float, float) #1
27 %0 = tail call float @llvm.nvvm.sin.approx.ftz.f(float %a)
28 %1 = tail call float @llvm.nvvm.cos.approx.ftz.f(float %a)
29 %2 = tail call float @llvm.nvvm.div.approx.ftz.f(float %0, float %1)
Dinline-asm.ll6 ; CHECK: ex2.approx.ftz.f32 %f{{[0-9]+}}, %f{{[0-9]+}}
7 %0 = call float asm "ex2.approx.ftz.f32 $0, $1;", "=f,f"(float %x)
Dnvvm-reflect-module-flag.ll13 !0 = !{i32 4, !"nvvm-reflect-ftz", i32 42}
Dfast-math.ll34 ; CHECK: add.ftz.f32
/external/eigen/bench/tensors/
DREADME9 …gpu.cu benchmark_main.cc -I ../../ -std=c++11 -O2 -DNDEBUG -use_fast_math -ftz=true -arch compute_…
12 …gpu.cu benchmark_main.cc -I ../../ -std=c++11 -O2 -DNDEBUG -use_fast_math -ftz=true -arch compute_…
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td212 // Also defines ftz (flush subnormal inputs and results to sign-preserving
230 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a, $b;"),
236 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a, $b;"),
270 !strconcat(OpcStr, ".rn.ftz.f32 \t$dst, $a, $b;"),
276 !strconcat(OpcStr, ".rn.ftz.f32 \t$dst, $a, $b;"),
294 // instructions: <OpcStr>.f64, <OpcStr>.f32, and <OpcStr>.ftz.f32 (flush
301 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a;"),
325 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
330 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
335 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
[all …]
DNVPTXVector.td283 def V4F32_ftz : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "ftz.f32")>, OpNode,
285 def V2F32_ftz : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "ftz.f32")>, OpNode,
526 defm F32MAD_ftz : VMAD<"mad.ftz.f32", V4F32Regs, V2F32Regs, fadd, fmul,
528 defm F32FMA_ftz : VMAD<"fma.rn.ftz.f32", V4F32Regs, V2F32Regs, fadd, fmul,
538 def V4F32Div_prec_ftz : VecBinaryOp<V4AsmStr<"div.rn.ftz.f32">, fdiv, V4F32Regs,
540 def V2F32Div_prec_ftz : VecBinaryOp<V2AsmStr<"div.rn.ftz.f32">, fdiv, V2F32Regs,
546 def V2F32Div_ftz : VecBinaryOp<V2AsmStr<"div.full.ftz.f32">, fdiv, V2F32Regs,
548 def V4F32Div_ftz : VecBinaryOp<V4AsmStr<"div.full.ftz.f32">, fdiv, V4F32Regs,
558 def VNegv2f32_ftz : VecUnaryOp<V2UnaryStr<"neg.ftz.f32">, fnegpat, V2F32Regs,
560 def VNegv4f32_ftz : VecUnaryOp<V4UnaryStr<"neg.ftz.f32">, fnegpat, V4F32Regs,
DNVPTXIntrinsics.td229 def INT_NVVM_FMIN_FTZ_F : F_MATH_2<"min.ftz.f32 \t$dst, $src0, $src1;",
234 def INT_NVVM_FMAX_FTZ_F : F_MATH_2<"max.ftz.f32 \t$dst, $src0, $src1;",
256 def INT_NVVM_MUL_RN_FTZ_F : F_MATH_2<"mul.rn.ftz.f32 \t$dst, $src0, $src1;",
260 def INT_NVVM_MUL_RZ_FTZ_F : F_MATH_2<"mul.rz.ftz.f32 \t$dst, $src0, $src1;",
264 def INT_NVVM_MUL_RM_FTZ_F : F_MATH_2<"mul.rm.ftz.f32 \t$dst, $src0, $src1;",
268 def INT_NVVM_MUL_RP_FTZ_F : F_MATH_2<"mul.rp.ftz.f32 \t$dst, $src0, $src1;",
292 : F_MATH_2<"div.approx.ftz.f32 \t$dst, $src0, $src1;", Float32Regs,
297 def INT_NVVM_DIV_RN_FTZ_F : F_MATH_2<"div.rn.ftz.f32 \t$dst, $src0, $src1;",
301 def INT_NVVM_DIV_RZ_FTZ_F : F_MATH_2<"div.rz.ftz.f32 \t$dst, $src0, $src1;",
305 def INT_NVVM_DIV_RM_FTZ_F : F_MATH_2<"div.rm.ftz.f32 \t$dst, $src0, $src1;",
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_emit_nvc0.cpp544 if (i->ftz) in emitFMAD()
571 assert(!i->ftz); in emitDMAD()
600 if (i->ftz) in emitFMUL()
603 assert(!neg && !i->saturate && !i->ftz && !i->postFactor); in emitFMUL()
620 assert(!i->ftz); in emitDMUL()
673 if (i->ftz) in emitFADD()
694 assert(!i->ftz); in emitDADD()
1011 if (i->ftz) in emitMINMAX()
1102 if (i->ftz) in emitCVT()
1190 if (i->ftz) in emitSET()
[all …]
Dnv50_ir.cpp571 ftz = 0; in init()
760 i->ftz = ftz; in clone()
Dnv50_ir_emit_gk110.cpp167 #define FTZ_(b) if (i->ftz) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
514 assert(!i->ftz); in emitDMAD()
595 assert(!i->ftz); in emitDMUL()
673 assert(!i->ftz); in emitDADD()
Dnv50_ir_print.cpp636 PRINT("%s%s", dnz ? "dnz " : (ftz ? "ftz " : ""), DataTypeStr[dType]); in print()
Dnv50_ir.h871 unsigned ftz : 1; // flush denormal to zero variable
Dnv50_ir_peephole.cpp3205 this->ftz != that->ftz || in isActionEqual()
Dnv50_ir_emit_gm107.cpp463 emitField(pos, len, insn->dnz << 1 | insn->ftz); in emitFMZ()
Dnv50_ir_lowering_nvc0.cpp115 i->ftz = true; in handleFTZ()
/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/timezone/
DTimeZoneTest.java1344 TimeZone ftz = TimeZone.getTimeZone(funkyName); in TestOddTimeZoneNames() local
1347 String fdn = ftz.getDisplayName(); in TestOddTimeZoneNames()
1348 long fro = ftz.getRawOffset(); in TestOddTimeZoneNames()
1349 long fds = ftz.getDSTSavings(); in TestOddTimeZoneNames()
1350 boolean fdy = ftz.useDaylightTime(); in TestOddTimeZoneNames()
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/timezone/
DTimeZoneTest.java1343 TimeZone ftz = TimeZone.getTimeZone(funkyName); in TestOddTimeZoneNames() local
1346 String fdn = ftz.getDisplayName(); in TestOddTimeZoneNames()
1347 long fro = ftz.getRawOffset(); in TestOddTimeZoneNames()
1348 long fds = ftz.getDSTSavings(); in TestOddTimeZoneNames()
1349 boolean fdy = ftz.useDaylightTime(); in TestOddTimeZoneNames()
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen2862 nvvm_add_rm_ftz_f, // llvm.nvvm.add.rm.ftz.f
2865 nvvm_add_rn_ftz_f, // llvm.nvvm.add.rn.ftz.f
2868 nvvm_add_rp_ftz_f, // llvm.nvvm.add.rp.ftz.f
2871 nvvm_add_rz_ftz_f, // llvm.nvvm.add.rz.ftz.f
2910 nvvm_ceil_ftz_f, // llvm.nvvm.ceil.ftz.f
2916 nvvm_cos_approx_ftz_f, // llvm.nvvm.cos.approx.ftz.f
2918 nvvm_d2f_rm_ftz, // llvm.nvvm.d2f.rm.ftz
2920 nvvm_d2f_rn_ftz, // llvm.nvvm.d2f.rn.ftz
2922 nvvm_d2f_rp_ftz, // llvm.nvvm.d2f.rp.ftz
2924 nvvm_d2f_rz_ftz, // llvm.nvvm.d2f.rz.ftz
[all …]
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen2856 nvvm_add_rm_ftz_f, // llvm.nvvm.add.rm.ftz.f
2859 nvvm_add_rn_ftz_f, // llvm.nvvm.add.rn.ftz.f
2862 nvvm_add_rp_ftz_f, // llvm.nvvm.add.rp.ftz.f
2865 nvvm_add_rz_ftz_f, // llvm.nvvm.add.rz.ftz.f
2904 nvvm_ceil_ftz_f, // llvm.nvvm.ceil.ftz.f
2910 nvvm_cos_approx_ftz_f, // llvm.nvvm.cos.approx.ftz.f
2912 nvvm_d2f_rm_ftz, // llvm.nvvm.d2f.rm.ftz
2914 nvvm_d2f_rn_ftz, // llvm.nvvm.d2f.rn.ftz
2916 nvvm_d2f_rp_ftz, // llvm.nvvm.d2f.rp.ftz
2918 nvvm_d2f_rz_ftz, // llvm.nvvm.d2f.rz.ftz
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen2862 nvvm_add_rm_ftz_f, // llvm.nvvm.add.rm.ftz.f
2865 nvvm_add_rn_ftz_f, // llvm.nvvm.add.rn.ftz.f
2868 nvvm_add_rp_ftz_f, // llvm.nvvm.add.rp.ftz.f
2871 nvvm_add_rz_ftz_f, // llvm.nvvm.add.rz.ftz.f
2910 nvvm_ceil_ftz_f, // llvm.nvvm.ceil.ftz.f
2916 nvvm_cos_approx_ftz_f, // llvm.nvvm.cos.approx.ftz.f
2918 nvvm_d2f_rm_ftz, // llvm.nvvm.d2f.rm.ftz
2920 nvvm_d2f_rn_ftz, // llvm.nvvm.d2f.rn.ftz
2922 nvvm_d2f_rp_ftz, // llvm.nvvm.d2f.rp.ftz
2924 nvvm_d2f_rz_ftz, // llvm.nvvm.d2f.rz.ftz
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen2862 nvvm_add_rm_ftz_f, // llvm.nvvm.add.rm.ftz.f
2865 nvvm_add_rn_ftz_f, // llvm.nvvm.add.rn.ftz.f
2868 nvvm_add_rp_ftz_f, // llvm.nvvm.add.rp.ftz.f
2871 nvvm_add_rz_ftz_f, // llvm.nvvm.add.rz.ftz.f
2910 nvvm_ceil_ftz_f, // llvm.nvvm.ceil.ftz.f
2916 nvvm_cos_approx_ftz_f, // llvm.nvvm.cos.approx.ftz.f
2918 nvvm_d2f_rm_ftz, // llvm.nvvm.d2f.rm.ftz
2920 nvvm_d2f_rn_ftz, // llvm.nvvm.d2f.rn.ftz
2922 nvvm_d2f_rp_ftz, // llvm.nvvm.d2f.rp.ftz
2924 nvvm_d2f_rz_ftz, // llvm.nvvm.d2f.rz.ftz
[all …]
/external/llvm/docs/
DNVPTXUsage.rst953 ex2.approx.ftz.f32 %f88,%f89;
/external/trappy/doc/
DPlotter.ipynb399 …0u3evZuZM2fi8XiwLIu9e/dy11130a1bN2bOnElGRgYRERGMGjWK\noKAgABITE0lKSiIgIID+/ftz+eWXO5xCRETKi7q6VQKT…