| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 923 unsigned RotAmt = V.getConstantOperandVal(1); in getValueBits()
936 unsigned ShiftAmt = V.getConstantOperandVal(1); in getValueBits()
952 unsigned ShiftAmt = V.getConstantOperandVal(1); in getValueBits()
968 uint64_t Mask = V.getConstantOperandVal(1); in getValueBits()
3056 int Elt = N->getConstantOperandVal(0); in Select()
3057 int EltSize = N->getConstantOperandVal(1); in Select()
3165 uint64_t PM = O.getConstantOperandVal(2); in combineToCMPB()
3166 uint64_t PAlt = O.getConstantOperandVal(3); in combineToCMPB()
3179 O.getConstantOperandVal(1) != 0) { in combineToCMPB()
3193 if (Op0.getConstantOperandVal(1) != Bits-8) in combineToCMPB()
[all …]
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 139 inline uint64_t getConstantOperandVal(unsigned i) const;
531 uint64_t getConstantOperandVal(unsigned Num) const;
781 inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
782 return Node->getConstantOperandVal(i);
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 615 if (N->getConstantOperandVal(1)) in PreprocessISelDAG()
927 int ScaleLog = 8 - Shift.getConstantOperandVal(1); in foldMaskAndShiftToExtract()
976 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in foldMaskedShiftToScaledMask()
1036 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in foldMaskAndShiftToScale()
1226 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1); in matchAddressRecursively()
1377 uint64_t Mask = N.getConstantOperandVal(1); in matchAddressRecursively()
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| D | X86ISelLowering.cpp | 5505 Offset = Ptr.getConstantOperandVal(1); in LowerAsSplatVectorLoad()
14741 unsigned ShAmt = Op->getConstantOperandVal(1); in EmitTest()
15607 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); in LowerSETCC()
16675 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); in LowerBRCOND()
16693 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); in LowerBRCOND()
16706 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); in LowerBRCOND()
16960 unsigned Align = Op.getConstantOperandVal(3); in LowerVAARG()
26310 N->getConstantOperandVal(1) == 0) { in combineExtractVectorElt()
27078 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B && in checkBoolTestSetCCCombine()
27083 CC = X86::CondCode(SetCC.getConstantOperandVal(0)); in checkBoolTestSetCCCombine()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 166 inline uint64_t getConstantOperandVal(unsigned i) const;
663 uint64_t getConstantOperandVal(unsigned Num) const;
880 inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
881 return Node->getConstantOperandVal(i);
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 250 const unsigned Align = N->getConstantOperandVal(3); in ExpandRes_VAARG()
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| D | LegalizeFloatTypes.cpp | 531 N->getConstantOperandVal(3)); in SoftenFloatRes_VAARG()
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| D | SelectionDAG.cpp | 2598 Operand.getConstantOperandVal(1) == 0 && in getNode()
5844 uint64_t SDNode::getConstantOperandVal(unsigned Num) const { in getConstantOperandVal() function in SDNode
6556 FrameOffset = Ptr.getConstantOperandVal(1); in InferPtrAlignment()
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| D | DAGCombiner.cpp | 5548 bool IsTrunc = N->getConstantOperandVal(1) == 1 && in visitFP_ROUND()
5549 N0.getNode()->getConstantOperandVal(1) == 1; in visitFP_ROUND()
5598 && N0.getNode()->getConstantOperandVal(1) == 1) { in visitFP_EXTEND()
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| D | LegalizeIntegerTypes.cpp | 703 N->getConstantOperandVal(3)); in PromoteIntRes_VAARG()
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| D | LegalizeDAG.cpp | 3166 unsigned Align = Node->getConstantOperandVal(3); in ExpandNode()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 597 if (Op.getConstantOperandVal(0) > 0) in LowerFRAMEADDR()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 306 const unsigned Align = N->getConstantOperandVal(3); in ExpandRes_VAARG()
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| D | InstrEmitter.cpp | 763 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos); in EmitMachineNode()
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| D | SelectionDAG.cpp | 1823 unsigned Align = Node->getConstantOperandVal(3); in expandVAArg()
3187 Operand.getConstantOperandVal(1) == 0 && in getNode()
6873 uint64_t SDNode::getConstantOperandVal(unsigned Num) const { in getConstantOperandVal() function in SDNode
7045 FrameOffset = Ptr.getConstantOperandVal(1); in InferPtrAlignment()
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| D | LegalizeFloatTypes.cpp | 697 N->getConstantOperandVal(3)); in SoftenFloatRes_VAARG()
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| D | DAGCombiner.cpp | 9153 const bool NIsTrunc = N->getConstantOperandVal(1) == 1; in visitFP_ROUND()
9154 const bool N0IsTrunc = N0.getNode()->getConstantOperandVal(1) == 1; in visitFP_ROUND()
9227 && N0.getNode()->getConstantOperandVal(1) == 1) { in visitFP_EXTEND()
13206 unsigned Idx = N->getConstantOperandVal(1); in visitEXTRACT_SUBVECTOR()
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1089 uint64_t depth = Op.getConstantOperandVal(0); in LowerFRAMEADDR()
1120 uint64_t depth = Op.getConstantOperandVal(0); in LowerRETURNADDR()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 1387 (SetCC->getConstantOperandVal(1) == 1 && in LowerBRCOND()
3109 unsigned OldDmask = Node->getConstantOperandVal(DmaskIdx); in adjustWritemask()
3125 Lane = SubIdx2Lane(I->getConstantOperandVal(1)); in adjustWritemask()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 1413 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), SDLoc(Op), in lowerMSASplatImm()
1592 Op->getConstantOperandVal(3)); in lowerINTRINSIC_WO_CHAIN()
1605 Op->getConstantOperandVal(3)); in lowerINTRINSIC_WO_CHAIN()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4919 Offset = Ptr.getConstantOperandVal(1); in LowerAsSplatVectorLoad()
8403 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); in LowerSETCC()
8856 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); in LowerBRCOND()
8874 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); in LowerBRCOND()
8887 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); in LowerBRCOND()
9057 unsigned Align = Op.getConstantOperandVal(3); in LowerVAARG()
12893 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); in PerformCMOVCombine()
13257 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); in CMPEQCombine()
13258 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); in CMPEQCombine()
14065 unsigned X86CC = N->getConstantOperandVal(0); in PerformSETCCCombine()
[all …]
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| D | X86ISelDAGToDAG.cpp | 496 if (N->getConstantOperandVal(1)) in PreprocessISelDAG()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3674 isPowerOf2_64(LHS.getConstantOperandVal(1))) { in LowerBR_CC()
3676 uint64_t Mask = LHS.getConstantOperandVal(1); in LowerBR_CC()
3690 isPowerOf2_64(LHS.getConstantOperandVal(1))) { in LowerBR_CC()
3692 uint64_t Mask = LHS.getConstantOperandVal(1); in LowerBR_CC()
4322 unsigned Align = Op.getConstantOperandVal(3); in LowerVAARG()
7393 uint64_t TruncMask = N->getConstantOperandVal(1); in isDesirableToCommuteWithShift()
7833 ShiftAmount = N->getConstantOperandVal(1); in findEXTRHalf()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2660 uint64_t depth = Op.getConstantOperandVal(0); in LowerFRAMEADDR()
2677 uint64_t depth = Op.getConstantOperandVal(0); in LowerRETURNADDR()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1113 MemN->getConstantOperandVal(MemN->getNumOperands() - 1) == 1)) { in SelectAddrMode6()
|