| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
401 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { in rewriteT2FrameIndex()
573 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg); in scheduleTwoAddrSource()
589 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg); in scheduleTwoAddrSource()
610 return llvm::getInstrPredicate(MI, PredReg); in getITInstrPredicate()
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| D | ARMLoadStoreOptimizer.cpp | 528 llvm::getInstrPredicate(MI, MyPredReg) == Pred && in isMatchingDecrement()
551 llvm::getInstrPredicate(MI, MyPredReg) == Pred && in isMatchingIncrement()
689 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg); in MergeBaseUpdateLSMultiple()
844 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg); in MergeBaseUpdateLoadStore()
1098 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg); in FixInvalidRegPairOp()
1209 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MBBI, PredReg); in LoadStoreMultipleOpti()
1568 Pred = llvm::getInstrPredicate(Op0, PredReg); in CanFormLdStDWord()
1761 if (llvm::getInstrPredicate(MI, PredReg) != ARMCC::AL) in RescheduleLoadStoreInstrs()
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| D | Thumb2SizeReduction.cpp | 534 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
615 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
706 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
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| D | ARMBaseInstrInfo.h | 338 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| D | Thumb1RegisterInfo.cpp | 413 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { in rewriteFrameIndex()
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| D | ARMConstantIslandPass.cpp | 1655 ARMCC::CondCodes Pred = llvm::getInstrPredicate(Br.MI, PredReg); in OptimizeThumb2Branches()
1673 Pred = llvm::getInstrPredicate(CmpMI, PredReg); in OptimizeThumb2Branches()
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| D | ARMExpandPseudoInsts.cpp | 648 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg); in ExpandMOV32BitImm()
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| D | ARMBaseInstrInfo.cpp | 1433 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate() function in llvm
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 61 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo()
469 if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL) { in rewriteT2FrameIndex()
642 return getInstrPredicate(MI, PredReg); in getITInstrPredicate()
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| D | ARMLoadStoreOptimizer.cpp | 861 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg); in MergeOpsUpdate()
1145 getInstrPredicate(MI, MIPredReg) != Pred || in isIncrementOrDecrement()
1212 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in MergeBaseUpdateLSMultiple()
1354 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in MergeBaseUpdateLoadStore()
1451 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in MergeBaseUpdateLSDouble()
1611 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in FixInvalidRegPairOp()
1717 ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg); in LoadStoreMultipleOpti()
2124 Pred = getInstrPredicate(*Op0, PredReg); in CanFormLdStDWord()
2318 if (getInstrPredicate(MI, PredReg) != ARMCC::AL) in RescheduleLoadStoreInstrs()
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| D | Thumb2SizeReduction.cpp | 648 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
753 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceTo2Addr()
849 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceToNarrow()
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| D | ARMBaseInstrInfo.h | 454 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
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| D | ARMConstantIslandPass.cpp | 1945 ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg); in optimizeThumb2Branches()
1963 Pred = getInstrPredicate(*CmpMI, PredReg); in optimizeThumb2Branches()
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| D | ARMBaseInstrInfo.cpp | 1721 ARMCC::CondCodes P = getInstrPredicate(*CmpMI, PredReg); in isProfitableToIfCvt()
1776 ARMCC::CondCodes llvm::getInstrPredicate(const MachineInstr &MI, in getInstrPredicate() function in llvm
1809 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
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| D | ARMExpandPseudoInsts.cpp | 669 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ExpandMOV32BitImm()
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