| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | PrologEpilogInserter.cpp | 253 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in calculateCalleeSavedRegisters()
321 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
348 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
396 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
447 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyReplacePhysRegs.cpp | 83 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); in runOnMachineFunction()
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| D | WebAssemblyInstrInfo.cpp | 61 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
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| /external/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 47 if (TRI.getMinimalPhysRegClass(DstR.Reg) != in interpretAsCopy()
48 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
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| D | HexagonVLIWPacketizer.cpp | 279 const TargetRegisterClass* RC = HRI->getMinimalPhysRegClass(DepReg); in isCallDependent()
594 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc); in canPromoteToNewValueStore()
606 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst); in canPromoteToNewValueStore()
1248 RC = HRI->getMinimalPhysRegClass(DepReg); in isLegalToPacketizeTogether()
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| D | HexagonFrameLowering.cpp | 1091 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); in insertCSRSpillsInBlock()
1144 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); in insertCSRRestoresInBlock()
1323 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg); in assignCalleeSavedSpillSlots()
1335 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R); in assignCalleeSavedSpillSlots()
1896 return HRI.getMinimalPhysRegClass(R.Reg); in optimizeSpillSlots()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 122 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize(); in estimateStackSize()
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| D | MipsSEFrameLowering.cpp | 243 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2; in expandCopyACC()
812 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
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| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetRegisterInfo.cpp | 55 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { in getMinimalPhysRegClass() function in TargetRegisterInfo
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreFrameLowering.cpp | 296 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
322 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /external/llvm/lib/CodeGen/ |
| D | StackMaps.cpp | 139 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg()); in parseOperand()
233 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); in createLiveOutReg()
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| D | PrologEpilogInserter.cpp | 358 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
484 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
513 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
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| D | TargetRegisterInfo.cpp | 128 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const { in getMinimalPhysRegClass() function in TargetRegisterInfo
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 172 return &getRegBankFromRegClass(*TRI.getMinimalPhysRegClass(Reg)); in getRegBank()
370 RC = TRI.getMinimalPhysRegClass(Reg); in getSizeInBits()
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 133 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8; in AddMachineRegPiece()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreFrameLowering.cpp | 439 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
467 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 302 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 344 getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 571 TRI->getMinimalPhysRegClass(Reg, VT); in ListScheduleBottomUp()
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| D | ScheduleDAGSDNodes.cpp | 120 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo)); in CheckForPhysRegDependency()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 1196 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
1222 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 582 TRI->getMinimalPhysRegClass(Reg, VT); in ListScheduleBottomUp()
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| D | ScheduleDAGSDNodes.cpp | 134 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo)); in CheckForPhysRegDependency()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 1873 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
1941 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
1985 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 1770 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
1915 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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