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Searched refs:getRegsAvailable (Results 1 – 7 of 7) sorted by relevance

/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DRegisterScavenging.h103 BitVector getRegsAvailable(const TargetRegisterClass *RC);
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterScavenging.cpp251 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { in getRegsAvailable() function in RegScavenger
349 BitVector Available = getRegsAvailable(RC); in scavengeRegister()
/external/llvm/include/llvm/CodeGen/
DRegisterScavenging.h110 BitVector getRegsAvailable(const TargetRegisterClass *RC);
/external/llvm/lib/CodeGen/
DRegisterScavenging.cpp268 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { in getRegsAvailable() function in RegScavenger
366 BitVector Available = getRegsAvailable(RC); in scavengeRegister()
/external/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp507 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID)); in scavengeRegister()
510 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID)); in scavengeRegister()
/external/llvm/lib/Target/Mips/
DMips16InstrInfo.cpp363 BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass); in loadImmediate()
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp625 BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass : in findScratchRegister()