| /external/llvm/lib/Target/AMDGPU/ |
| D | SILowerControlFlow.cpp | 453 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef())); in emitLoadM0FromVGPRLoop()
462 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef())); in emitLoadM0FromVGPRLoop()
536 .addReg(Idx->getReg(), getUndefRegState(Idx->isUndef())) in loadM0()
540 .addReg(Idx->getReg(), getUndefRegState(Idx->isUndef())); in loadM0()
643 .addReg(Reg, getUndefRegState(SrcVec->isUndef())); in indirectSrc()
650 .addReg(Reg, getUndefRegState(SrcVec->isUndef())) in indirectSrc()
679 .addReg(Val->getReg(), getUndefRegState(Val->isUndef())) in indirectDst()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 384 inline unsigned getUndefRegState(bool B) { in getUndefRegState() function
401 getUndefRegState(RegOp.isUndef()) | in getRegState()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 258 inline unsigned getUndefRegState(bool B) { in getUndefRegState() function
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1057 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1062 .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef)) in InsertLDR_STR()
1063 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1118 getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef)) in FixInvalidRegPairOp()
1120 getKillRegState(OddDeadKill) | getUndefRegState(OddUndef)); in FixInvalidRegPairOp()
|
| D | ARMExpandPseudoInsts.cpp | 577 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | in ExpandLaneOp()
|
| /external/llvm/lib/CodeGen/ |
| D | MachineInstrBundle.cpp | 213 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 484 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
486 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
488 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
490 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
567 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | in ExpandLaneOp()
|
| D | ARMLoadStoreOptimizer.cpp | 1561 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1566 .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef)) in InsertLDR_STR()
1567 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1631 getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef)) in FixInvalidRegPairOp()
1633 getKillRegState(OddDeadKill) | getUndefRegState(OddUndef)); in FixInvalidRegPairOp()
|
| D | ARMBaseInstrInfo.cpp | 4354 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI))) in setExecutionDomain()
4390 .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI))) in setExecutionDomain()
4424 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
4428 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
4443 MIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
4447 MIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegStackify.cpp | 554 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in MoveAndTeeForMultiUse()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 615 unsigned Flags1 = getUndefRegState(Cond[1].isUndef()); in InsertBranch()
618 unsigned Flags2 = getUndefRegState(Cond[2].isUndef()); in InsertBranch()
629 unsigned Flags = getUndefRegState(RO.isUndef()); in InsertBranch()
652 unsigned Flags = getUndefRegState(RO.isUndef()); in InsertBranch()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 166 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); in emitSPUpdate()
|
| D | X86InstrInfo.cpp | 2959 getUndefRegState(MO.isUndef())); in unfoldMemoryOperand()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 2815 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) in convertToThreeAddress()
2857 getKillRegState(isKill) | getUndefRegState(isUndef)); in convertToThreeAddress()
2889 .addReg(SrcReg, getUndefRegState(isUndef) | in convertToThreeAddress()
2999 .addReg(SrcReg, getUndefRegState(isUndef) | in convertToThreeAddress()
6439 getUndefRegState(ImpOp.isUndef())); in unfoldMemoryOperand()
|
| D | X86FrameLowering.cpp | 297 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); in emitSPUpdate()
|