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Searched refs:halfword (Results 1 – 25 of 62) sorted by relevance

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/external/llvm/test/CodeGen/Hexagon/
Dcombine_ir.ll5 ; CHECK-LABEL: halfword:
8 define void @halfword(i16* nocapture %a) nounwind {
Dbit-extractu-half.ll2 ; Pick lsr (in bit-simplification) for extracting high halfword.
/external/libavc/common/arm/
Dih264_iquant_itrans_recon_dc_a9.s125 ldrsh r8, [r0] @load pi2_src[0], SH for signed halfword load
126 ldrh r6, [r6] @load pu2_weight_mat[0] , H for unsigned halfword load
127 ldrh r5, [r5] @load pu2_iscal_mat[0] , H for unsigned halfword load
140 ldrsheq r10, [r0] @ Loads signed halfword pi2_src[0], if r9==1
244 ldrsh r8, [r0] @load pi2_src[0], SH for signed halfword load
245 ldrh r6, [r6] @load pu2_weight_mat[0] , H for unsigned halfword load
246 ldrh r5, [r5] @load pu2_iscal_mat[0] , H for unsigned halfword load
Dih264_ihadamard_scaling_a9.s105 ldrh r6, [r3] @ load pu2_weight_mat[0] , H for unsigned halfword load
106 ldrh r7, [r2] @ load pu2_iscal_mat[0] , H for unsigned halfword load
/external/llvm/test/CodeGen/AArch64/
Dldst-opt.ll7 %s.halfword = type { i16, i16 }
14 %struct.halfword = type { %padding, %s.halfword }
59 declare void @bar_halfword(%s.halfword*, i16)
61 define void @load-pre-indexed-halfword(%struct.halfword* %ptr) nounwind {
62 ; CHECK-LABEL: load-pre-indexed-halfword
65 %a = getelementptr inbounds %struct.halfword, %struct.halfword* %ptr, i64 0, i32 1, i32 0
69 %c = getelementptr inbounds %struct.halfword, %struct.halfword* %ptr, i64 0, i32 1
70 tail call void @bar_halfword(%s.halfword* %c, i16 %add)
74 define void @store-pre-indexed-halfword(%struct.halfword* %ptr, i16 %val) nounwind {
75 ; CHECK-LABEL: store-pre-indexed-halfword
[all …]
/external/llvm/test/CodeGen/Mips/cconv/
Dmemory-layout.ll23 @halfword = global i16 258, align 1
36 ; ALL-LABEL: halfword:
38 ; ALL: .size halfword, 2
/external/llvm/test/CodeGen/SystemZ/
Dint-move-05.ll44 ; Check the next halfword up, which should use STHY instead of STH.
64 ; Check the next halfword up, which needs separate address logic.
96 ; Check the next halfword down, which needs separate address logic.
Dint-mul-01.ll29 ; Check the next halfword up, which should use MHY instead of MH.
53 ; Check the next halfword up, which needs separate address logic.
91 ; Check the next halfword down, which needs separate address logic.
Dint-add-01.ll29 ; Check the next halfword up, which should use AHY instead of AH.
53 ; Check the next halfword up, which needs separate address logic.
91 ; Check the next halfword down, which needs separate address logic.
Dvec-const-10.ll29 ; Test a halfword-granularity replicate with the lowest useful value.
37 ; Test a halfword-granularity replicate with an arbitrary value.
45 ; Test a halfword-granularity replicate with the highest useful value.
Dint-sub-07.ll29 ; Check the next halfword up, which should use SHY instead of SH.
53 ; Check the next halfword up, which needs separate address logic.
91 ; Check the next halfword down, which needs separate address logic.
Dvec-const-09.ll29 ; Test a halfword-granularity replicate with the lowest useful value.
37 ; Test a halfword-granularity replicate with an arbitrary value.
45 ; Test a halfword-granularity replicate with the highest useful value.
Dvec-const-12.ll29 ; Test a halfword-granularity replicate with the lowest useful value.
37 ; Test a halfword-granularity replicate with an arbitrary value.
45 ; Test a halfword-granularity replicate with the highest useful value.
Dvec-const-08.ll32 ; Test a halfword-granularity replicate with the lowest useful value.
41 ; Test a halfword-granularity replicate with an arbitrary value.
50 ; Test a halfword-granularity replicate with the highest useful value.
Dvec-const-11.ll32 ; Test a halfword-granularity replicate with the lowest useful value.
41 ; Test a halfword-granularity replicate with an arbitrary value.
50 ; Test a halfword-granularity replicate with the highest useful value.
Dint-conv-05.ll1 ; Test sign extensions from a halfword to an i32.
46 ; Check the next halfword up, which needs LHY rather than LH.
68 ; Check the next halfword up, which needs separate address logic.
103 ; Check the next halfword down, which needs separate address logic.
Dint-cmp-01.ll33 ; Check the next halfword up, which should use CHY instead of CH.
61 ; Check the next halfword up, which needs separate address logic.
105 ; Check the next halfword down, which needs separate address logic.
Dvec-const-07.ll38 ; Test a halfword-granularity replicate with the lowest useful value.
49 ; Test a halfword-granularity replicate with an arbitrary value.
60 ; Test a halfword-granularity replicate with the highest useful value.
Dint-conv-06.ll1 ; Test zero extensions from a halfword to an i32. The tests here
56 ; Check the next halfword up, which needs separate address logic.
91 ; Check the next halfword down, which needs separate address logic.
Dint-conv-08.ll1 ; Test zero extensions from a halfword to an i64.
55 ; Check the next halfword up, which needs separate address logic.
90 ; Check the next halfword down, which needs separate address logic.
Dint-conv-07.ll1 ; Test sign extensions from a halfword to an i64.
46 ; Check the next halfword up, which needs separate address logic.
81 ; Check the next halfword down, which needs separate address logic.
Dint-cmp-04.ll33 ; Check the next halfword up, which needs separate address logic.
77 ; Check the next halfword down, which needs separate address logic.
/external/llvm/test/MC/Disassembler/Hexagon/
Dmemop.txt22 # Operation on memory halfword
Dld.txt128 # Load halfword
150 # Load halfword conditionally
236 # Load unsigned halfword
258 # Load unsigned halfword conditionally
/external/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td41 // is in the high (1) or low (0) word. The other halfword is 0x0000,
43 // halfword is 0xFFFF, and shifts (`AAA' = 111), for which the constant is
481 // If `YS' = 01 (halfword Store):
484 // If `YS' = 00 (halfword load): Rr <- Memory(ea)

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