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/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt206 # Vector absolute value halfwords
218 # Vector absolute difference halfwords
226 # Vector add halfwords
234 # Vector add halfwords with saturate and pack to unsigned bytes
244 # Vector reduce add halfwords
262 # Vector average halfwords
317 # Vector maximum halfwords
323 # Vector reduce maximum halfwords
347 # Vector minimum halfwords
353 # Vector reduce minimum halfwords
[all …]
Dalu32_alu.txt58 # Vector add halfwords
66 # Vector average halfwords
74 # Vector subtract halfwords
Dxtype_mpy.txt96 # Multiply signed halfwords
194 # Multiply unsigned halfwords
352 # Vector multiply halfwords
364 # Vector multiply halfwords with round and pack
370 # Vector multiply halfwords signed by unsigned
380 # Vector reduce multiply halfwords
396 # Vector polynomial multiply halfwords
Dxtype_shift.txt210 # Vector shift halfwords by immediate
218 # Vector arithmetic shift halfwords with round
222 # Vector arithmetic shift halfwords with saturate and pack
228 # Vector shift halfwords by register
Dalu32_perm.txt38 # Pack high and low halfwords
Dxtype_perm.txt74 # Vector splat halfwords
Dxtype_complex.txt4 # Complex add/sub halfwords
Dxtype_pred.txt84 # Vector compare halfwords
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV4.td32 // Vector multiply halfwords, signed by unsigned
41 // Vector polynomial multiply halfwords
72 // Vector reduce add unsigned halfwords
130 // Complex add/sub halfwords/words
152 // Vector reduce maximum halfwords
160 // Vector reduce minimum halfwords
DHexagonIntrinsicsV3.td19 // Vector reduce add unsigned halfwords
DHexagonIntrinsics.td223 // MPYS / Multipy signed/unsigned halfwords
274 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
335 // Multiply signed/unsigned halfwords with and without saturation and rounding
367 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
424 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
478 // Vector reduce halfwords
509 // Vector multiply even halfwords with accumulation
826 // Vector add, subtract, average halfwords
921 // ALU64 - Vector compare halfwords
949 // Vector multiply halfwords
[all …]
DHexagonInstrInfoVector.td92 // four halfwords of 64-bits destination register.
170 // Vector shift halfwords by register
DHexagonInstrInfoV4.td1973 // Complex add/sub halfwords/words
2062 // Vector reduce conditional negate halfwords
2277 // Vector reduce add unsigned halfwords
2286 // Vector reduce maximum halfwords
2294 // Vector reduce minimum halfwords
2534 // Vector multiply halfwords, signed by unsigned
2543 // Vector polynomial multiply halfwords
2602 // Vector compare halfwords
2740 // Vector reduce maximum halfwords
2750 // Vector reduce minimum halfwords
DHexagonInstrInfo.td988 // Vector compare halfwords
2306 // MPYS / Multipy signed/unsigned halfwords
2391 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2484 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2556 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2592 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
2926 // Vector reduce halfwords:
2933 // Used for complex multiply real or imaginary, dual multiply and even halfwords
3002 // Vector multiply even halfwords with accumulation
3019 // Template Class -- Multiply signed/unsigned halfwords with and without
[all …]
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dalu32_alu.ll125 ; Vector add halfwords
147 ; Vector average halfwords
169 ; Vector subtract halfwords
Dxtype_alu.ll466 ; Subtract halfwords
559 ; Vector absolute value halfwords
589 ; Vector absolute difference halfwords
605 ; Vector add halfwords
627 ; Vector add halfwords with saturate and pack to unsigned bytes
650 ; Vector reduce add halfwords
695 ; Vector average halfwords
854 ; Vector maximum halfwords
869 ; Vector reduce maximum halfwords
914 ; Vector minimum halfwords
[all …]
Dalu32_perm.ll101 ; Pack high and low halfwords
Dxtype_mpy.ll158 ; Multiply signed halfwords
775 ; Multiply unsigned halfwords
1371 ; Vector multiply even halfwords
1407 ; Vector multiply halfwords
1443 ; Vector multiply halfwords signed by unsigned
1472 ; Vector reduce multiply halfwords
1516 ; Vector polynomial multiply halfwords
Dxtype_perm.ll175 ; Vector splat halfwords
Dxtype_pred.ll203 ; Vector compare halfwords
Dxtype_complex.ll7 ; Complex add/sub halfwords
Dxtype_shift.ll640 ; Vector shift halfwords by immediate
662 ; Vector shift halfwords by register
/external/llvm/test/CodeGen/PowerPC/
Dvec_extload.ll33 ; Same as v16si8_sext_in_reg, expands to load/store halfwords (lhz/sth).
/external/v8/src/s390/
Dassembler-s390-inl.h518 int32_t halfwords = (target - pc) / 2; // number of halfwords in set_target_address_at() local
519 instr_1 |= static_cast<uint32_t>(halfwords); in set_target_address_at()
Dassembler-s390.h765 int32_t halfwords = branch_offset(l) / 2; in b() local
766 brasl(r, Operand(halfwords)); in b()

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