Searched refs:isARMLowRegister (Results 1 – 16 of 16) sorted by relevance
52 isARMLowRegister(SrcReg))) && "Unknown regclass!"); in storeRegToStackSlot()56 isARMLowRegister(SrcReg))) { in storeRegToStackSlot()81 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()85 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
309 if (!isARMLowRegister(Reg)) in VerifyLowRegs()370 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA) in ReduceLoadStore()411 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()496 if (!isARMLowRegister(MI->getOperand(0).getReg())) in ReduceSpecial()599 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()608 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()694 if (Entry.LowRegs1 && !isARMLowRegister(Reg)) in ReduceToNarrow()
98 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()99 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()235 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
1577 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { in OptimizeThumb2Instructions()1584 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { in OptimizeThumb2Instructions()1676 isARMLowRegister(Reg)) { in OptimizeThumb2Branches()
1032 isARMLowRegister(Reg) || Reg == ARM::LR) { in processFunctionBeforeCalleeSavedScan()1061 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || in processFunctionBeforeCalleeSavedScan()
77 isARMLowRegister(SrcReg))) && "Unknown regclass!"); in storeRegToStackSlot()81 isARMLowRegister(SrcReg))) { in storeRegToStackSlot()103 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()107 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
371 if (!isARMLowRegister(Reg)) in VerifyLowRegs()442 assert(isARMLowRegister(Rt)); in ReduceLoadStore()443 assert(isARMLowRegister(Rn)); in ReduceLoadStore()470 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore()517 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()611 if (!isARMLowRegister(MI->getOperand(0).getReg())) in ReduceSpecial()712 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()713 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()737 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()746 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()[all …]
110 assert((isARMLowRegister(DestReg) || isVirtualRegister(DestReg)) && in emitLoadConstPool()129 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()130 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()143 if (!isARMLowRegister(DestReg) && !MRI.isVirtualRegister(DestReg)) in emitThumbRegPlusImmInReg()223 } else if (isARMLowRegister(DestReg)) { in emitThumbRegPlusImmediate()233 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
1852 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { in optimizeThumb2Instructions()1859 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { in optimizeThumb2Instructions()1966 isARMLowRegister(Reg)) { in optimizeThumb2Branches()
1673 isARMLowRegister(Reg) || Reg == ARM::LR) { in determineCalleeSaves()1702 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || in determineCalleeSaves()
701 if (isARMLowRegister(NewBase) && isARMLowRegister(Base) && in CreateLoadStoreMulti()
1723 isARMLowRegister(Reg)) in isProfitableToIfCvt()
773 return isARMLowRegister(Memory.BaseRegNum) && in isMemThumbRR()774 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); in isMemThumbRR()778 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs4()787 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs2()796 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs1()3698 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || in shouldOmitCCOutOperand()3699 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && in shouldOmitCCOutOperand()3705 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && in shouldOmitCCOutOperand()3706 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && in shouldOmitCCOutOperand()3727 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || in shouldOmitCCOutOperand()[all …]
210 static inline bool isARMLowRegister(unsigned Reg) { in isARMLowRegister() function
1281 return isARMLowRegister(Memory.BaseRegNum) && in isMemThumbRR()1282 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); in isMemThumbRR()1286 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs4()1295 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs2()1304 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs1()5672 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && in shouldOmitCCOutOperand()5673 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && in shouldOmitCCOutOperand()5699 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()5700 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()5701 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || in shouldOmitCCOutOperand()[all …]
193 static inline bool isARMLowRegister(unsigned Reg) { in isARMLowRegister() function