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Searched refs:isAssignedRegDep (Results 1 – 11 of 11) sorted by relevance

/external/llvm/lib/CodeGen/
DScheduleDAG.cpp350 if (I->isAssignedRegDep()) in dumpAll()
370 if (I->isAssignedRegDep()) in dumpAll()
607 if (I->isAssignedRegDep() && in WillCreateCycle()
DMachinePipeliner.cpp3696 if (S.isAssignedRegDep()) { in orderDependence()
3713 if (P.isAssignedRegDep()) { in orderDependence()
3830 if (SI.isAssignedRegDep()) in isValidSchedule()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp160 if (I->isAssignedRegDep()) { in ReleasePredecessors()
190 if (I->isAssignedRegDep()) { in ScheduleNodeBottomUp()
473 if (I->isAssignedRegDep()) { in DelayForLiveRegsBottomUp()
DScheduleDAGList.cpp133 assert(!I->isAssignedRegDep() && in ReleaseSuccessors()
DScheduleDAGRRList.cpp428 if (I->isAssignedRegDep()) { in ReleasePredecessors()
626 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) { in ScheduleNodeBottomUp()
679 if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){ in UnscheduleNodeBottomUp()
691 if (I->isAssignedRegDep()) { in UnscheduleNodeBottomUp()
1076 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU) in DelayForLiveRegsBottomUp()
1338 assert(!I->isAssignedRegDep() && in ReleaseSuccessors()
2641 if (!PI->isAssignedRegDep()) in canClobberReachingPhysRegUse()
2792 assert(!Edge.isAssignedRegDep()); in PrescheduleNodesWithMultipleUses()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGVLIW.cpp144 assert(!I->isAssignedRegDep() && in releaseSuccessors()
DScheduleDAGFast.cpp166 if (I->isAssignedRegDep()) { in ReleasePredecessors()
196 if (I->isAssignedRegDep()) { in ScheduleNodeBottomUp()
484 if (I->isAssignedRegDep()) { in DelayForLiveRegsBottomUp()
DScheduleDAGRRList.cpp530 if (I->isAssignedRegDep()) { in ReleasePredecessors()
743 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) { in ScheduleNodeBottomUp()
812 if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){ in UnscheduleNodeBottomUp()
852 if (Succ.isAssignedRegDep()) { in UnscheduleNodeBottomUp()
866 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg && in UnscheduleNodeBottomUp()
1270 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU) in DelayForLiveRegsBottomUp()
2706 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()
2864 assert(!Edge.isAssignedRegDep()); in PrescheduleNodesWithMultipleUses()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DScheduleDAG.cpp321 if (I->isAssignedRegDep()) in dumpAll()
575 if (I->isAssignedRegDep() && in WillCreateCycle()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DScheduleDAG.h195 bool isAssignedRegDep() const { in isAssignedRegDep() function
/external/llvm/include/llvm/CodeGen/
DScheduleDAG.h211 bool isAssignedRegDep() const { in isAssignedRegDep() function