| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 192 assert(MO.isImm() && "did not expect relocated expression"); in getMachineOpValue()
203 if (MO.isImm()) in getLdStUImm12OpValue()
224 if (MO.isImm()) in getAdrLabelOpValue()
255 if (MO.isImm()) in getAddSubImmOpValue()
277 if (MO.isImm()) in getCondBranchTargetOpValue()
299 if (MO.isImm()) in getLoadLiteralOpValue()
327 if (MO.isImm()) in getMoveWideImmOpValue()
347 if (MO.isImm()) in getTestBranchTargetOpValue()
369 if (MO.isImm()) in getBranchTargetOpValue()
395 assert(MO.isImm() && "Expected an immediate value for the shift amount!"); in getVecShifterOpValue()
[all …]
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 55 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
101 assert(InstIn.getOperand(2).isImm()); in LowerDins()
103 assert(InstIn.getOperand(3).isImm()); in LowerDins()
276 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTargetOpValue()
299 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValue1SImm16()
322 if (MO.isImm()) in getBranchTargetOpValueMMR6()
346 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTarget7OpValueMM()
368 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMMPC10()
390 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMM()
413 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTarget21OpValue()
[all …]
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| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 117 if (MCOp.isImm()) in getMachineOpValue()
148 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
156 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
197 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
203 if (Op2.isImm()) { in getRiMemoryOpValue()
233 assert(AluMCOp.isImm() && "Third operator is not immediate."); in getRrMemoryOpValue()
268 assert((Op2.isImm() || Op2.isExpr()) && in getSplsOpValue()
274 if (Op2.isImm()) { in getSplsOpValue()
295 if (MCOp.isReg() || MCOp.isImm()) in getCallTargetOpValue()
308 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCTargetDesc.cpp | 37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
43 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
50 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
57 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
58 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
68 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && in getITDeprecationInfo()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getDirectBrEncoding()
100 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getCondBrEncoding()
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getHA16Encoding()
122 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getLO16Encoding()
138 if (MO.isImm()) in getMemRIEncoding()
156 if (MO.isImm()) in getMemRIXEncoding()
187 assert(MO.isImm() && in getMachineOpValue()
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
224 if (MO.isImm()) in getMemRIEncoding()
243 if (MO.isImm()) in getMemRIXEncoding()
261 assert(MO.isImm()); in getMemRIX16Encoding()
276 assert(MO.isImm()); in getSPE8DisEncoding()
292 assert(MO.isImm()); in getSPE4DisEncoding()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUAsmPrinter.cpp | 67 } else if (MO.isImm()) { in printOperand()
152 assert(MI->getOperand(OpNo).isImm() && in printDFormAddr()
167 if (MI->getOperand(OpNo).isImm()) { in printAddr256K()
171 if (MI->getOperand(OpNo+1).isImm()) { in printAddr256K()
199 if (MI->getOperand(OpNo).isImm()) { in printSymbolHi()
208 if (MI->getOperand(OpNo).isImm()) { in printSymbolLo()
223 if (MI->getOperand(OpNo).isImm()) { in printROTHNeg7Imm()
234 assert(MI->getOperand(OpNo).isImm() && in printROTNeg7Imm()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 186 (Op.isImm() && Op.getImm() == 0)); in isZeroOperand()
247 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction()
266 else if (AluOffset.isImm()) in insertMergedInstruction()
302 if (Op2.isImm()) { in isSuitableAluInstr()
311 if (Offset.isImm() && in isSuitableAluInstr()
373 assert(AluOperand.isImm() && "Unexpected memory operator type"); in combineMemAluInBasicBlock()
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 145 assert(isImm() && "Invalid type access!"); in getImm()
177 bool isImm() const override { return Kind == IMMEDIATE; } in isImm() function
194 if (!isImm()) in isBrImm()
208 bool isCallTarget() { return isImm() || isToken(); } in isCallTarget()
211 if (!isImm()) in isHiImm16()
234 if (!isImm()) in isHiImm16And()
247 if (!isImm()) in isLoImm16()
271 if (!isImm()) in isLoImm16Signed()
295 if (!isImm()) in isLoImm16And()
308 if (!isImm()) in isImmShift()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/InstPrinter/ |
| D | MBlazeInstPrinter.cpp | 40 } else if (Op.isImm()) { in printOperand()
51 if (MO.isImm()) in printFSLImm()
60 if (MO.isImm()) in printUnsignedImm()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCCodeEmitter.cpp | 182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getDirectBrEncoding()
198 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getHA16Encoding()
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getLO16Encoding()
221 if (MO.isImm()) in getMemRIEncoding()
237 if (MO.isImm()) in getMemRIXEncoding()
256 assert(MO.isImm() && in getMachineOpValue()
|
| /external/llvm/lib/Target/Lanai/InstPrinter/ |
| D | LanaiInstPrinter.cpp | 152 else if (Op.isImm()) in printOperand()
163 if (Op.isImm()) { in printMemImmOperand()
177 if (Op.isImm()) { in printHi16ImmOperand()
189 if (Op.isImm()) { in printHi16AndImmOperand()
201 if (Op.isImm()) { in printLo16AndImmOperand()
226 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); in printMemoryImmediateOffset()
227 if (OffsetOp.isImm()) { in printMemoryImmediateOffset()
|
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 383 bool isImm = fieldFromInstruction(insn, 13, 1); in DecodeMem() local
388 if (isImm) in DecodeMem()
406 if (isImm) in DecodeMem()
540 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeJMPL() local
543 if (isImm) in DecodeJMPL()
559 if (isImm) in DecodeJMPL()
573 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeReturn() local
576 if (isImm) in DecodeReturn()
587 if (isImm) in DecodeReturn()
602 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeSWAP() local
[all …]
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86InstComments.cpp | 389 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
405 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
421 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
435 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
453 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
543 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
560 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
573 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
584 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
595 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
[all …]
|
| D | X86IntelInstPrinter.cpp | 126 if (Op.isImm()) in printPCRelImm()
149 } else if (Op.isImm()) { in printOperand()
187 if (!DispSpec.isImm()) { in printMemReference()
244 if (DispSpec.isImm()) { in printMemOffset()
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| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| D | SparcMCCodeEmitter.cpp | 123 if (MO.isImm()) in getMachineOpValue()
147 if (MO.isReg() || MO.isImm()) in getCallTargetOpValue()
182 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
195 if (MO.isReg() || MO.isImm()) in getBranchPredTargetOpValue()
207 if (MO.isReg() || MO.isImm()) in getBranchOnRegTargetOpValue()
|
| /external/llvm/lib/Target/BPF/InstPrinter/ |
| D | BPFInstPrinter.cpp | 58 } else if (Op.isImm()) { in printOperand()
71 if (OffsetOp.isImm()) in printMemOperand()
84 if (Op.isImm()) in printImm64Operand()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/InstPrinter/ |
| D | MSP430InstPrinter.cpp | 37 if (Op.isImm()) in printPCRelImmOperand()
51 } else if (Op.isImm()) { in printOperand()
79 assert(Disp.isImm() && "Expected immediate in displacement field"); in printSrcMemOperand()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 150 if (MI->getOperand(OpNo).isImm()) in printS16X4ImmOperand()
158 if (!MI->getOperand(OpNo).isImm()) in printBranchOperand()
204 if (MI->getOperand(OpNo).isImm()) in printMemRegImmShifted()
259 if (Op.isImm()) { in printOperand()
270 if (MI->getOperand(OpNo).isImm()) in printSymbolLo()
287 if (MI->getOperand(OpNo).isImm()) in printSymbolHi()
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| D | MSP430InstPrinter.cpp | 38 if (Op.isImm()) in printPCRelImmOperand()
52 } else if (Op.isImm()) { in printOperand()
81 assert(Disp.isImm() && "Expected immediate in displacement field"); in printSrcMemOperand()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 58 if (FoldOp->isImm()) { in FoldCandidate()
67 bool isImm() const { in isImm() function
105 if (Fold.isImm()) { in updateOperand()
205 bool FoldingImm = OpToFold.isImm(); in foldOperand()
319 bool FoldingImm = OpToFold.isImm(); in runOnMachineFunction()
371 if (!Fold.isImm()) { in runOnMachineFunction()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 81 if (Op.isImm()) in print_pcrel_imm()
95 } else if (Op.isImm()) { in printOperand()
121 if (DispSpec.isImm()) { in printMemReference()
|
| D | X86IntelInstPrinter.cpp | 69 if (Op.isImm()) in print_pcrel_imm()
87 } else if (Op.isImm()) { in printOperand()
126 if (!DispSpec.isImm()) { in printMemReference()
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 214 bool isImm() const override { in isImm() function in __anon80afaadf0111::SystemZOperand
217 bool isImm(int64_t MinValue, int64_t MaxValue) const { in isImm() function in __anon80afaadf0111::SystemZOperand
333 bool isU1Imm() const { return isImm(0, 1); } in isU1Imm()
334 bool isU2Imm() const { return isImm(0, 3); } in isU2Imm()
335 bool isU3Imm() const { return isImm(0, 7); } in isU3Imm()
336 bool isU4Imm() const { return isImm(0, 15); } in isU4Imm()
337 bool isU6Imm() const { return isImm(0, 63); } in isU6Imm()
338 bool isU8Imm() const { return isImm(0, 255); } in isU8Imm()
339 bool isS8Imm() const { return isImm(-128, 127); } in isS8Imm()
340 bool isU12Imm() const { return isImm(0, 4095); } in isU12Imm()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXISelDAGToDAG.cpp | 56 bool isImm(const SDValue &operand);
200 isImm(Addr.getOperand(0)) || isImm(Addr.getOperand(1))) in SelectADDRrr()
244 if (isImm(Addr)) { in SelectADDRri()
337 bool PTXDAGToDAGISel::isImm(const SDValue &operand) { in isImm() function in PTXDAGToDAGISel
|