| /external/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 215 HaveRegParm = Locs.back().isRegLoc(); in getRemainingRegParmsForType()
221 if (Locs[I].isRegLoc()) in getRemainingRegParmsForType()
275 bool RegLoc1 = Loc1.isRegLoc(); in resultsCompatible()
276 if (RegLoc1 != Loc2.isRegLoc()) in resultsCompatible()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 116 bool isRegLoc() const { return !isMem; } in isRegLoc() function
121 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 82 assert(VA.isRegLoc() && "Not yet implemented"); in lowerFormalArguments()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 143 bool isRegLoc() const { return !isMem; } in isRegLoc() function
148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 184 if (VA.isRegLoc()) { in LowerFormalArguments()
252 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
329 if (VA.isRegLoc()) { in LowerCall()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 308 if (VA.isRegLoc()) { in LowerCCCArguments()
428 if (VA.isRegLoc()) { in LowerCCCCallTo()
574 if (RVLocs[i].isRegLoc()) in LowerReturn()
584 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 172 if (VA.isRegLoc()) { in LowerFormalArguments()
290 if (VA.isRegLoc()) in LowerCall()
373 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 103 if (RVLocs[i].isRegLoc()) in LowerReturn()
112 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
183 if (VA.isRegLoc()) { in LowerFormalArguments()
478 if (VA.isRegLoc()) { in LowerCall()
482 if (NextVA.isRegLoc()) { in LowerCall()
515 if (VA.isRegLoc()) { in LowerCall()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 741 if (VA.isRegLoc()) { in LowerCall()
895 if (VA.isRegLoc()) { in LowerFormalArguments()
1027 if (RVLocs[i].isRegLoc()) in LowerReturn()
1036 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 324 if (VA.isRegLoc()) { in LowerCCCArguments()
409 if (RVLocs[i].isRegLoc()) in LowerReturn()
418 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
491 if (VA.isRegLoc()) { in LowerCCCCallTo()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1894 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1900 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1975 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1986 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2115 if (!VA.isRegLoc()) in SelectRet()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 233 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
316 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
415 if (VA.isRegLoc()) { in LowerFormalArguments_32()
602 if (VA.isRegLoc()) { in LowerFormalArguments_64()
874 if (VA.isRegLoc()) { in LowerCall_32()
878 if (NextVA.isRegLoc()) { in LowerCall_32()
911 if (VA.isRegLoc()) { in LowerCall_32()
1109 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1222 if (VA.isRegLoc()) { in LowerCall_64()
1260 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && in LowerCall_64()
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 946 if (VA.isRegLoc()) { in LowerCCCCallTo()
1102 if (VA.isRegLoc()) { in LowerCCCArguments()
1225 if (RVLocs[i].isRegLoc()) in LowerReturn()
1234 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1078 if (VA.isRegLoc()) { in LowerCallResult()
1173 if (VA.isRegLoc()) { in LowerCCCCallTo()
1310 if (VA.isRegLoc()) { in LowerCCCArguments()
1482 if (VA.isRegLoc()) in LowerReturn()
1511 if (!VA.isRegLoc()) in LowerReturn()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1634 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1646 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false; in ProcessCallArgs()
1754 if (!VA.isRegLoc()) in SelectRet()
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| D | ARMISelLowering.cpp | 1199 if (NextVA.isRegLoc()) in PassF64ArgInRegs()
1308 if (VA.isRegLoc()) { in LowerCall()
1321 } else if (VA.isRegLoc()) { in LowerCall()
1695 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) in IsEligibleForTailCallOptimization()
1699 if (RVLocs1[i].isRegLoc()) { in IsEligibleForTailCallOptimization()
1742 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
1744 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
1747 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
1749 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
1752 } else if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
[all …]
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 434 if (VA.isRegLoc()) { in LowerCCCArguments()
531 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
603 if (VA.isRegLoc()) { in LowerCCCCallTo()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 442 if (VA.isRegLoc()) { in LowerCCCArguments()
540 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
673 if (VA.isRegLoc()) { in LowerCCCCallTo()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2012 if (Subtarget->isABI_O32() && VA.isRegLoc()) { in LowerCall()
2043 if (VA.isRegLoc()) { in LowerCall()
2276 if (VA.isRegLoc()) { in LowerFormalArguments()
2439 if (RVLocs[i].isRegLoc()) in LowerReturn()
2448 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1302 !VA.isRegLoc() || VA.needsCustom()) in processCallArgs()
1410 assert(VA.isRegLoc() && "Can only return in registers!"); in finishCall()
1653 assert(VA.isRegLoc() && "Can only return in registers!"); in SelectRet()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1173 if (VA.isRegLoc() && !VA.needsCustom()) { in processCallArgs()
1474 if (!VA.isRegLoc()) in selectRet()
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| D | MipsISelLowering.cpp | 2749 if (VA.isRegLoc()) { in LowerCall()
2802 if (VA.isRegLoc()) { in LowerCall()
2912 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
3061 bool IsRegLoc = VA.isRegLoc(); in LowerFormalArguments()
3232 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 784 if (VA.isRegLoc()) in LowerCall()
1099 if ( (VA.isRegLoc() && !Flags.isByVal()) in LowerFormalArguments()
1100 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) { in LowerFormalArguments()
1155 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) { in LowerFormalArguments()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 745 if (!VA.isRegLoc()) in X86SelectRet()
1722 if (VA.isRegLoc()) { in DoSelectCall()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 280 if (VA.isRegLoc()) { in LowerCall()
|