Searched refs:lane_size (Results 1 – 4 of 4) sorted by relevance
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 1804 unsigned lane_size = vt.GetLaneSizeInBytes(); in LoadStoreStructSingle() local
1805 VIXL_ASSERT(lane < (kQRegSizeInBytes / lane_size)); in LoadStoreStructSingle()
1809 lane *= lane_size; in LoadStoreStructSingle()
1810 if (lane_size == 8) lane++; in LoadStoreStructSingle()
1817 switch (lane_size) { in LoadStoreStructSingle()
1828 VIXL_ASSERT(lane_size == 8); in LoadStoreStructSingle()
3161 int lane_size = vn.GetLaneSizeInBytes(); in dup() local
3163 switch (lane_size) { in dup()
3174 VIXL_ASSERT(lane_size == 8); in dup()
3213 int lane_size = vd.GetLaneSizeInBytes(); in ins() local
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| D | simulator-aarch64.cc | 472 unsigned reg_size, unsigned lane_size) { in GetPrintRegisterFormatForSize() argument
473 VIXL_ASSERT(reg_size >= lane_size); in GetPrintRegisterFormatForSize()
476 if (reg_size != lane_size) { in GetPrintRegisterFormatForSize()
490 switch (lane_size) { in GetPrintRegisterFormatForSize()
825 int lane_size = 1 << lane_size_log2; in PrintVRegister() local
836 PrintVRegisterFPHelper(code, lane_size, lane_count); in PrintVRegister()
949 int lane_size = GetPrintRegLaneSizeInBytes(format); in PrintVWrite() local
951 PrintVRegisterRawHelper(reg_code, reg_size, lane_size * lane); in PrintVWrite()
953 PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane); in PrintVWrite()
4046 int lane_size = LaneSizeInBytesFromFormat(vf); in NEONLoadStoreMultiStructHelper() local
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| D | logic-aarch64.cc | 783 int lane_size = LaneSizeInBitsFromFormat(vform); in add() local
804 dst.SetInt(vform, i, ur >> (64 - lane_size)); in add()
1190 int lane_size = LaneSizeInBitsFromFormat(vform); in sub() local
1211 dst.SetInt(vform, i, ur >> (64 - lane_size)); in sub()
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| D | simulator-aarch64.h | 1459 unsigned lane_size);
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