| /external/llvm/test/MC/Mips/ |
| D | mips-expansions.s | 144 # CHECK-BE: lbu $8, 1($zero) # encoding: [0x90,0x08,0x00,0x01]
148 # CHECK-LE: lbu $8, 0($zero) # encoding: [0x00,0x00,0x08,0x90]
154 # CHECK-BE: lbu $8, 3($zero) # encoding: [0x90,0x08,0x00,0x03]
158 # CHECK-LE: lbu $8, 2($zero) # encoding: [0x02,0x00,0x08,0x90]
165 # CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
170 # CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
176 # CHECK-BE: lbu $8, -32767($zero) # encoding: [0x90,0x08,0x80,0x01]
180 # CHECK-LE: lbu $8, -32768($zero) # encoding: [0x00,0x80,0x08,0x90]
187 # CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
192 # CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
[all …]
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| D | mips64-expansions.s | 104 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
105 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
116 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
117 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
127 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
128 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
139 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
140 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
151 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
152 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
[all …]
|
| D | mips-memory-instructions.s | 28 # CHECK: lbu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x90]
38 lbu $4, 4($5)
|
| D | micromips-loadstore-instructions.s | 13 # CHECK-EL: lbu $6, 8($4) # encoding: [0xc4,0x14,0x08,0x00]
59 # CHECK-EB: lbu $6, 8($4) # encoding: [0x14,0xc4,0x00,0x08]
102 lbu $6, 8($4)
|
| /external/llvm/test/CodeGen/Mips/ |
| D | unalignedload.ll | 20 ; MIPS32-EL-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]])
21 ; MIPS32-EL-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]])
25 ; MIPS32-EB-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]])
26 ; MIPS32-EB-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]])
45 ; MIPS32-EL-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]])
46 ; MIPS32-EL-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]])
47 ; MIPS32-EL-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]])
55 ; MIPS32-EB-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]])
56 ; MIPS32-EB-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]])
57 ; MIPS32-EB-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]])
[all …]
|
| D | load-store-left-right.ll | 255 ; ALL-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
257 ; ALL-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
271 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
273 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
275 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
277 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
288 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
290 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
292 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
294 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
[all …]
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| D | misha.ll | 29 ; 16: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
30 ; 16: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
|
| D | lbu1.ll | 11 ; 16: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
|
| D | mips64intldst.ll | 70 ; CHECK-N64: lbu ${{[0-9]+}}, 0($[[R0]])
73 ; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]])
|
| /external/libjpeg-turbo/simd/ |
| D | jsimd_mips_dspr2.S | 62 lbu t3, 0(t2)
68 lbu t3, 0(t2)
73 lbu t4, 0(t4)
74 lbu t7, 0(t7)
75 lbu t8, 0(t8)
104 lbu t3, 0(t2)
109 lbu t4, 0(t4)
110 lbu t7, 0(t7)
111 lbu t8, 0(t8)
150 lbu \r, \r_offs(\inptr)
[all …]
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| /external/valgrind/none/tests/mips64/ |
| D | load_store.stdout.exp-BE | 3073 lbu :: offset: 0x0, out: 0x0
3074 lbu :: offset: 0x1, out: 0x0
3075 lbu :: offset: 0x2, out: 0x0
3076 lbu :: offset: 0x3, out: 0x0
3077 lbu :: offset: 0x4, out: 0x0
3078 lbu :: offset: 0x5, out: 0x0
3079 lbu :: offset: 0x6, out: 0x0
3080 lbu :: offset: 0x7, out: 0x0
3081 lbu :: offset: 0x8, out: 0x9
3082 lbu :: offset: 0x9, out: 0x82
[all …]
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| D | load_store.stdout.exp-LE | 3073 lbu :: offset: 0x0, out: 0x0
3074 lbu :: offset: 0x1, out: 0x0
3075 lbu :: offset: 0x2, out: 0x0
3076 lbu :: offset: 0x3, out: 0x0
3077 lbu :: offset: 0x4, out: 0x0
3078 lbu :: offset: 0x5, out: 0x0
3079 lbu :: offset: 0x6, out: 0x0
3080 lbu :: offset: 0x7, out: 0x0
3081 lbu :: offset: 0x8, out: 0x6e
3082 lbu :: offset: 0x9, out: 0x3b
[all …]
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | loadstoreconv.ll | 39 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
59 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
80 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
82 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
137 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
151 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
170 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
172 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
| D | logopm.ll | 39 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
40 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
61 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
85 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
110 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
111 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
132 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
154 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
179 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
180 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
[all …]
|
| D | retabi.ll | 63 ; CHECK: lbu $2, 0($[[REG_C_ADDR]])
77 ; CHECK: lbu $[[REG_C:[0-9]+]], 0($[[REG_C_ADDR]])
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | return.ll | 33 ; O32-DAG: lbu $2, %lo(byte)([[R1]])
35 ; N32-DAG: lbu $2, %lo(byte)([[R1]])
37 ; N64-DAG: lbu $2, 0([[R1]])
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | unalignedload.ll | 15 ; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]])
27 ; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]])
|
| D | mips64intldst.ll | 68 ; CHECK-N64: lbu ${{[0-9]+}}, 0($[[R0]])
71 ; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]])
|
| /external/swiftshader/third_party/LLVM/test/MC/MBlaze/ |
| D | mblaze_memory.s | 9 # CHECK: lbu
12 lbu r1, r2, r3
|
| /external/llvm/test/MC/Mips/micromips/ |
| D | invalid.s | 127 lbu $32, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
128 lbu $4, -32769($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
129 lbu $4, 32768($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
130 lbu $4, 8($32) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
|
| /external/v8/src/regexp/mips/ |
| D | regexp-macro-assembler-mips.cc | 259 __ lbu(a3, MemOperand(a0, 0)); in CheckNotBackReferenceIgnoreCase() local
261 __ lbu(t0, MemOperand(a2, 0)); in CheckNotBackReferenceIgnoreCase() local
405 __ lbu(a3, MemOperand(a0, 0)); in CheckNotBackReference() local
407 __ lbu(t0, MemOperand(a2, 0)); in CheckNotBackReference() local
498 __ lbu(a0, FieldMemOperand(a0, ByteArray::kHeaderSize)); in CheckBitInTable() local
578 __ lbu(a0, MemOperand(a0, 0)); in CheckSpecialCharacterClass() local
591 __ lbu(a0, MemOperand(a0, 0)); in CheckSpecialCharacterClass() local
1286 __ lbu(current_character(), MemOperand(t5, 0)); in LoadCurrentCharacterUnchecked() local
|
| /external/v8/src/regexp/mips64/ |
| D | regexp-macro-assembler-mips64.cc | 295 __ lbu(a3, MemOperand(a0, 0)); in CheckNotBackReferenceIgnoreCase() local
297 __ lbu(a4, MemOperand(a2, 0)); in CheckNotBackReferenceIgnoreCase() local
435 __ lbu(a3, MemOperand(a0, 0)); in CheckNotBackReference() local
437 __ lbu(a4, MemOperand(a2, 0)); in CheckNotBackReference() local
528 __ lbu(a0, FieldMemOperand(a0, ByteArray::kHeaderSize)); in CheckBitInTable() local
608 __ lbu(a0, MemOperand(a0, 0)); in CheckSpecialCharacterClass() local
621 __ lbu(a0, MemOperand(a0, 0)); in CheckSpecialCharacterClass() local
1323 __ lbu(current_character(), MemOperand(t1, 0)); in LoadCurrentCharacterUnchecked() local
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | extractelement.ll | 19 ; ALL: lbu $2, 0([[EPTR]])
|
| /external/valgrind/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-mips32-LE | 140 lbu $t0, 0($t1) :: rt 0x0000001f
141 lbu $t0, 4($t1) :: rt 0x00000000
142 lbu $t0, 8($t1) :: rt 0x00000003
143 lbu $t0, 12($t1) :: rt 0x000000ff
144 lbu $t0, 16($t1) :: rt 0x0000002f
145 lbu $t0, 20($t1) :: rt 0x0000002b
146 lbu $t0, 24($t1) :: rt 0x0000002b
147 lbu $t0, 28($t1) :: rt 0x0000002a
148 lbu $t0, 32($t1) :: rt 0x0000003e
149 lbu $t0, 36($t1) :: rt 0x0000003c
[all …]
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| D | MIPS32int.stdout.exp-mips32-BE | 140 lbu $t0, 0($t1) :: rt 0x00000012
141 lbu $t0, 4($t1) :: rt 0x00000000
142 lbu $t0, 8($t1) :: rt 0x00000000
143 lbu $t0, 12($t1) :: rt 0x000000ff
144 lbu $t0, 16($t1) :: rt 0x00000023
145 lbu $t0, 20($t1) :: rt 0x00000024
146 lbu $t0, 24($t1) :: rt 0x00000025
147 lbu $t0, 28($t1) :: rt 0x00000026
148 lbu $t0, 32($t1) :: rt 0x0000003f
149 lbu $t0, 36($t1) :: rt 0x0000003e
[all …]
|