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Searched refs:ld2r (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-simd-ldst-one-elem.s29 ld2r { v0.16b, v1.16b }, [x0]
30 ld2r { v15.8h, v16.8h }, [x15]
31 ld2r { v31.4s, v0.4s }, [sp]
32 ld2r { v0.2d, v1.2d }, [x0]
33 ld2r { v0.8b, v1.8b }, [x0]
34 ld2r { v15.4h, v16.4h }, [x15]
35 ld2r { v31.2s, v0.2s }, [sp]
36 ld2r { v31.1d, v0.1d }, [sp]
190 ld2r { v0.16b, v1.16b }, [x0], #2
191 ld2r { v15.8h, v16.8h }, [x15], #4
[all …]
Darm64-simd-ldst.s904 ld2r: label
905 ld2r.8b {v4, v5}, [x2]
906 ld2r.8b {v4, v5}, [x2], x3
907 ld2r.16b {v4, v5}, [x2]
908 ld2r.16b {v4, v5}, [x2], x3
909 ld2r.4h {v4, v5}, [x2]
910 ld2r.4h {v4, v5}, [x2], x3
911 ld2r.8h {v4, v5}, [x2]
912 ld2r.8h {v4, v5}, [x2], x3
913 ld2r.2s {v4, v5}, [x2]
[all …]
Dneon-diagnostics.s4194 ld2r {v31.4s, v0.2s}, [sp]
4253 ld2r {v0.2d, v1.2d}, [x0], #7
/external/llvm/test/CodeGen/AArch64/
Darm64-ld1.ll557 ; CHECK: ld2r.8b { v0, v1 }, [x0]
559 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A)
581 declare %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8*) nounwind readonly
588 ; CHECK: ld2r.16b { v0, v1 }, [x0]
590 %tmp2 = call %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A)
612 declare %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8*) nounwind readonly
619 ; CHECK: ld2r.4h { v0, v1 }, [x0]
621 %tmp2 = call %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* %A)
643 declare %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16*) nounwind readonly
650 ; CHECK: ld2r.8h { v0, v1 }, [x0]
[all …]
Dfp16-vector-load-store.ll224 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half*)
227 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half*)
234 ; CHECK: ld2r { v0.4h, v1.4h }, [x0]
236 %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half* %a)
261 ; CHECK: ld2r { v0.8h, v1.8h }, [x0]
263 %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half* %a)
Darm64-indexed-vector-ldst.ll2128 ;CHECK: ld2r.16b { v0, v1 }, [x0], #2
2129 %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A)
2137 ;CHECK: ld2r.16b { v0, v1 }, [x0], x{{[0-9]+}}
2138 %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A)
2144 declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8*) nounwind readonly
2149 ;CHECK: ld2r.8b { v0, v1 }, [x0], #2
2150 %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A)
2158 ;CHECK: ld2r.8b { v0, v1 }, [x0], x{{[0-9]+}}
2159 %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A)
2165 declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8*) nounwind readonly
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1074 # CHECK: ld2r.8b { v1, v2 }, [x1]
1075 # CHECK: ld2r.8b { v1, v2 }, [x1], x2
1076 # CHECK: ld2r.16b { v1, v2 }, [x1]
1077 # CHECK: ld2r.16b { v1, v2 }, [x1], x2
1078 # CHECK: ld2r.4h { v1, v2 }, [x1]
1079 # CHECK: ld2r.4h { v1, v2 }, [x1], x2
1080 # CHECK: ld2r.8h { v1, v2 }, [x1]
1081 # CHECK: ld2r.8h { v1, v2 }, [x1], x2
1082 # CHECK: ld2r.2s { v1, v2 }, [x1]
1083 # CHECK: ld2r.2s { v1, v2 }, [x1], x2
[all …]
Dneon-instructions.txt2084 # CHECK: ld2r { v31.4s, v0.4s }, [sp]
2085 # CHECK: ld2r { v0.2d, v1.2d }, [x0]
2126 # CHECK: ld2r { v31.4s, v0.4s }, [sp], #8
2127 # CHECK: ld2r { v0.2d, v1.2d }, [x0], #16
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc996 __ ld2r(v26.V16B(), v27.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
997 __ ld2r(v21.V16B(), v22.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
998 __ ld2r(v5.V16B(), v6.V16B(), MemOperand(x1, 2, PostIndex)); in GenerateTestSequenceNEON() local
999 __ ld2r(v26.V1D(), v27.V1D(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1000 __ ld2r(v14.V1D(), v15.V1D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
1001 __ ld2r(v23.V1D(), v24.V1D(), MemOperand(x1, 16, PostIndex)); in GenerateTestSequenceNEON() local
1002 __ ld2r(v11.V2D(), v12.V2D(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1003 __ ld2r(v29.V2D(), v30.V2D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
1004 __ ld2r(v15.V2D(), v16.V2D(), MemOperand(x1, 16, PostIndex)); in GenerateTestSequenceNEON() local
1005 __ ld2r(v26.V2S(), v27.V2S(), MemOperand(x0)); in GenerateTestSequenceNEON() local
[all …]
/external/vixl/test/test-trace-reference/
Dlog-disasm862 0x~~~~~~~~~~~~~~~~ 4d60c01a ld2r {v26.16b, v27.16b}, [x0]
863 0x~~~~~~~~~~~~~~~~ 4de2c035 ld2r {v21.16b, v22.16b}, [x1], x2
864 0x~~~~~~~~~~~~~~~~ 4dffc025 ld2r {v5.16b, v6.16b}, [x1], #2
865 0x~~~~~~~~~~~~~~~~ 0d60cc1a ld2r {v26.1d, v27.1d}, [x0]
866 0x~~~~~~~~~~~~~~~~ 0de2cc2e ld2r {v14.1d, v15.1d}, [x1], x2
867 0x~~~~~~~~~~~~~~~~ 0dffcc37 ld2r {v23.1d, v24.1d}, [x1], #16
868 0x~~~~~~~~~~~~~~~~ 4d60cc0b ld2r {v11.2d, v12.2d}, [x0]
869 0x~~~~~~~~~~~~~~~~ 4de2cc3d ld2r {v29.2d, v30.2d}, [x1], x2
870 0x~~~~~~~~~~~~~~~~ 4dffcc2f ld2r {v15.2d, v16.2d}, [x1], #16
871 0x~~~~~~~~~~~~~~~~ 0d60c81a ld2r {v26.2s, v27.2s}, [x0]
[all …]
Dlog-disasm-colour862 0x~~~~~~~~~~~~~~~~ 4d60c01a ld2r {v26.16b, v27.16b}, [x0]
863 0x~~~~~~~~~~~~~~~~ 4de2c035 ld2r {v21.16b, v22.16b}, [x1], x2
864 0x~~~~~~~~~~~~~~~~ 4dffc025 ld2r {v5.16b, v6.16b}, [x1], #2
865 0x~~~~~~~~~~~~~~~~ 0d60cc1a ld2r {v26.1d, v27.1d}, [x0]
866 0x~~~~~~~~~~~~~~~~ 0de2cc2e ld2r {v14.1d, v15.1d}, [x1], x2
867 0x~~~~~~~~~~~~~~~~ 0dffcc37 ld2r {v23.1d, v24.1d}, [x1], #16
868 0x~~~~~~~~~~~~~~~~ 4d60cc0b ld2r {v11.2d, v12.2d}, [x0]
869 0x~~~~~~~~~~~~~~~~ 4de2cc3d ld2r {v29.2d, v30.2d}, [x1], x2
870 0x~~~~~~~~~~~~~~~~ 4dffcc2f ld2r {v15.2d, v16.2d}, [x1], #16
871 0x~~~~~~~~~~~~~~~~ 0d60c81a ld2r {v26.2s, v27.2s}, [x0]
[all …]
Dlog-all2146 0x~~~~~~~~~~~~~~~~ 4d60c01a ld2r {v26.16b, v27.16b}, [x0]
2149 0x~~~~~~~~~~~~~~~~ 4de2c035 ld2r {v21.16b, v22.16b}, [x1], x2
2153 0x~~~~~~~~~~~~~~~~ 4dffc025 ld2r {v5.16b, v6.16b}, [x1], #2
2157 0x~~~~~~~~~~~~~~~~ 0d60cc1a ld2r {v26.1d, v27.1d}, [x0]
2160 0x~~~~~~~~~~~~~~~~ 0de2cc2e ld2r {v14.1d, v15.1d}, [x1], x2
2164 0x~~~~~~~~~~~~~~~~ 0dffcc37 ld2r {v23.1d, v24.1d}, [x1], #16
2168 0x~~~~~~~~~~~~~~~~ 4d60cc0b ld2r {v11.2d, v12.2d}, [x0]
2171 0x~~~~~~~~~~~~~~~~ 4de2cc3d ld2r {v29.2d, v30.2d}, [x1], x2
2175 0x~~~~~~~~~~~~~~~~ 4dffcc2f ld2r {v15.2d, v16.2d}, [x1], #16
2179 0x~~~~~~~~~~~~~~~~ 0d60c81a ld2r {v26.2s, v27.2s}, [x0]
[all …]
/external/vixl/src/aarch64/
Dassembler-aarch64.h1934 void ld2r(const VRegister& vt, const VRegister& vt2, const MemOperand& src);
Dsimulator-aarch64.h1855 void ld2r(VectorFormat vform,
Dmacro-assembler-aarch64.h2564 ld2r(vt, vt2, src); in Ld2r()
Dsimulator-aarch64.cc4181 ld2r(vf, ReadVRegister(rt), ReadVRegister(rt2), addr); in NEONLoadStoreSingleStructHelper()
Dlogic-aarch64.cc457 void Simulator::ld2r(VectorFormat vform, in ld2r() function in vixl::aarch64::Simulator
Dassembler-aarch64.cc1608 void Assembler::ld2r(const VRegister& vt, in ld2r() function in vixl::aarch64::Assembler
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md2586 void ld2r(const VRegister& vt,
/external/valgrind/none/tests/arm64/
Dmemory.stdout.exp17920 ld2r {v17.2d , v18.2d }, [x5] with x5 = middle_of_block+3, x6=-5
17950 ld2r {v18.1d , v19.1d }, [x5] with x5 = middle_of_block+3, x6=-4
17980 ld2r {v19.4s , v20.4s }, [x5] with x5 = middle_of_block+3, x6=-3
18010 ld2r {v17.2s , v18.2s }, [x5] with x5 = middle_of_block+3, x6=-2
18040 ld2r {v18.8h , v19.8h }, [x5] with x5 = middle_of_block+3, x6=-1
18070 ld2r {v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=1
18100 ld2r {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+3, x6=2
18130 ld2r {v18.8b , v19.8b }, [x5] with x5 = middle_of_block+3, x6=3
18160 ld2r {v19.2d , v20.2d }, [x5], #16 with x5 = middle_of_block+3, x6=-5
18190 ld2r {v17.1d , v18.1d }, [x5], #16 with x5 = middle_of_block+3, x6=-4
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td5077 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen236 aarch64_neon_ld2r, // llvm.aarch64.neon.ld2r
6294 "llvm.aarch64.neon.ld2r",
14234 2, // llvm.aarch64.neon.ld2r
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen228 aarch64_neon_ld2r, // llvm.aarch64.neon.ld2r
6252 "llvm.aarch64.neon.ld2r",
14137 2, // llvm.aarch64.neon.ld2r
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen236 aarch64_neon_ld2r, // llvm.aarch64.neon.ld2r
6294 "llvm.aarch64.neon.ld2r",
14234 2, // llvm.aarch64.neon.ld2r
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen236 aarch64_neon_ld2r, // llvm.aarch64.neon.ld2r
6294 "llvm.aarch64.neon.ld2r",
14234 2, // llvm.aarch64.neon.ld2r

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