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Searched refs:ld3r (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-simd-ldst-one-elem.s46 ld3r { v0.16b, v1.16b, v2.16b }, [x0]
47 ld3r { v15.8h, v16.8h, v17.8h }, [x15]
48 ld3r { v31.4s, v0.4s, v1.4s }, [sp]
49 ld3r { v0.2d, v1.2d, v2.2d }, [x0]
50 ld3r { v0.8b, v1.8b, v2.8b }, [x0]
51 ld3r { v15.4h, v16.4h, v17.4h }, [x15]
52 ld3r { v31.2s, v0.2s, v1.2s }, [sp]
53 ld3r { v31.1d, v0.1d, v1.1d }, [sp]
207 ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9
208 ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6
[all …]
Darm64-simd-ldst.s958 ld3r: label
959 ld3r.8b {v4, v5, v6}, [x2]
960 ld3r.8b {v4, v5, v6}, [x2], x3
961 ld3r.16b {v4, v5, v6}, [x2]
962 ld3r.16b {v4, v5, v6}, [x2], x3
963 ld3r.4h {v4, v5, v6}, [x2]
964 ld3r.4h {v4, v5, v6}, [x2], x3
965 ld3r.8h {v4, v5, v6}, [x2]
966 ld3r.8h {v4, v5, v6}, [x2], x3
967 ld3r.2s {v4, v5, v6}, [x2]
[all …]
Dneon-diagnostics.s4195 ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
4254 ld3r {v15.4h, v16.4h, v17.4h}, [x15], #1
/external/llvm/test/CodeGen/AArch64/
Darm64-ld1.ll566 ; CHECK: ld3r.8b { v0, v1, v2 }, [x0]
568 %tmp2 = call %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
582 declare %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8*) nounwind readonly
597 ; CHECK: ld3r.16b { v0, v1, v2 }, [x0]
599 %tmp2 = call %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
613 declare %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8*) nounwind readonly
628 ; CHECK: ld3r.4h { v0, v1, v2 }, [x0]
630 %tmp2 = call %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* %A)
644 declare %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16*) nounwind readonly
659 ; CHECK: ld3r.8h { v0, v1, v2 }, [x0]
[all …]
Dfp16-vector-load-store.ll225 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half*)
228 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half*)
243 ; CHECK: ld3r { v0.4h, v1.4h, v2.4h }, [x0]
245 …%0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half* %a)
270 ; CHECK: ld3r { v0.8h, v1.8h, v2.8h }, [x0]
272 …%0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half* %a)
Darm64-indexed-vector-ldst.ll2376 ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], #3
2377 %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
2385 ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
2386 %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
2392 declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8*) nounwind readon…
2397 ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], #3
2398 %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
2406 ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
2407 %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
2413 declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8*) nounwind readonly
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1260 # CHECK: ld3r.8b { v1, v2, v3 }, [x1]
1261 # CHECK: ld3r.8b { v1, v2, v3 }, [x1], x2
1262 # CHECK: ld3r.16b { v1, v2, v3 }, [x1]
1263 # CHECK: ld3r.16b { v1, v2, v3 }, [x1], x2
1264 # CHECK: ld3r.4h { v1, v2, v3 }, [x1]
1265 # CHECK: ld3r.4h { v1, v2, v3 }, [x1], x2
1266 # CHECK: ld3r.8h { v1, v2, v3 }, [x1]
1267 # CHECK: ld3r.8h { v1, v2, v3 }, [x1], x2
1268 # CHECK: ld3r.2s { v1, v2, v3 }, [x1]
1269 # CHECK: ld3r.2s { v1, v2, v3 }, [x1], x2
[all …]
Dneon-instructions.txt2086 # CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0]
2087 # CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15]
2128 # CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
2129 # CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1053 __ ld3r(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1054 __ ld3r(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
1055 __ ld3r(v3.V16B(), v4.V16B(), v5.V16B(), MemOperand(x1, 3, PostIndex)); in GenerateTestSequenceNEON() local
1056 __ ld3r(v4.V1D(), v5.V1D(), v6.V1D(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1057 __ ld3r(v7.V1D(), v8.V1D(), v9.V1D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
1058 __ ld3r(v17.V1D(), v18.V1D(), v19.V1D(), MemOperand(x1, 24, PostIndex)); in GenerateTestSequenceNEON() local
1059 __ ld3r(v16.V2D(), v17.V2D(), v18.V2D(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1060 __ ld3r(v20.V2D(), v21.V2D(), v22.V2D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
1061 __ ld3r(v14.V2D(), v15.V2D(), v16.V2D(), MemOperand(x1, 24, PostIndex)); in GenerateTestSequenceNEON() local
1062 __ ld3r(v10.V2S(), v11.V2S(), v12.V2S(), MemOperand(x0)); in GenerateTestSequenceNEON() local
[all …]
/external/vixl/test/test-trace-reference/
Dlog-disasm919 0x~~~~~~~~~~~~~~~~ 4d40e018 ld3r {v24.16b, v25.16b, v26.16b}, [x0]
920 0x~~~~~~~~~~~~~~~~ 4dc2e038 ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
921 0x~~~~~~~~~~~~~~~~ 4ddfe023 ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
922 0x~~~~~~~~~~~~~~~~ 0d40ec04 ld3r {v4.1d, v5.1d, v6.1d}, [x0]
923 0x~~~~~~~~~~~~~~~~ 0dc2ec27 ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
924 0x~~~~~~~~~~~~~~~~ 0ddfec31 ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
925 0x~~~~~~~~~~~~~~~~ 4d40ec10 ld3r {v16.2d, v17.2d, v18.2d}, [x0]
926 0x~~~~~~~~~~~~~~~~ 4dc2ec34 ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
927 0x~~~~~~~~~~~~~~~~ 4ddfec2e ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
928 0x~~~~~~~~~~~~~~~~ 0d40e80a ld3r {v10.2s, v11.2s, v12.2s}, [x0]
[all …]
Dlog-disasm-colour919 0x~~~~~~~~~~~~~~~~ 4d40e018 ld3r {v24.16b, v25.16b, v26.16b}, [x0]
920 0x~~~~~~~~~~~~~~~~ 4dc2e038 ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
921 0x~~~~~~~~~~~~~~~~ 4ddfe023 ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
922 0x~~~~~~~~~~~~~~~~ 0d40ec04 ld3r {v4.1d, v5.1d, v6.1d}, [x0]
923 0x~~~~~~~~~~~~~~~~ 0dc2ec27 ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
924 0x~~~~~~~~~~~~~~~~ 0ddfec31 ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
925 0x~~~~~~~~~~~~~~~~ 4d40ec10 ld3r {v16.2d, v17.2d, v18.2d}, [x0]
926 0x~~~~~~~~~~~~~~~~ 4dc2ec34 ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
927 0x~~~~~~~~~~~~~~~~ 4ddfec2e ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
928 0x~~~~~~~~~~~~~~~~ 0d40e80a ld3r {v10.2s, v11.2s, v12.2s}, [x0]
[all …]
Dlog-all2388 0x~~~~~~~~~~~~~~~~ 4d40e018 ld3r {v24.16b, v25.16b, v26.16b}, [x0]
2392 0x~~~~~~~~~~~~~~~~ 4dc2e038 ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
2397 0x~~~~~~~~~~~~~~~~ 4ddfe023 ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
2402 0x~~~~~~~~~~~~~~~~ 0d40ec04 ld3r {v4.1d, v5.1d, v6.1d}, [x0]
2406 0x~~~~~~~~~~~~~~~~ 0dc2ec27 ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
2411 0x~~~~~~~~~~~~~~~~ 0ddfec31 ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
2416 0x~~~~~~~~~~~~~~~~ 4d40ec10 ld3r {v16.2d, v17.2d, v18.2d}, [x0]
2420 0x~~~~~~~~~~~~~~~~ 4dc2ec34 ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
2425 0x~~~~~~~~~~~~~~~~ 4ddfec2e ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
2430 0x~~~~~~~~~~~~~~~~ 0d40e80a ld3r {v10.2s, v11.2s, v12.2s}, [x0]
[all …]
/external/vixl/src/aarch64/
Dassembler-aarch64.h1950 void ld3r(const VRegister& vt,
Dsimulator-aarch64.h1870 void ld3r(VectorFormat vform,
Dmacro-assembler-aarch64.h2589 ld3r(vt, vt2, vt3, src); in Ld3r()
Dsimulator-aarch64.cc4191 ld3r(vf, ReadVRegister(rt), ReadVRegister(rt2), ReadVRegister(rt3), addr); in NEONLoadStoreSingleStructHelper()
Dlogic-aarch64.cc510 void Simulator::ld3r(VectorFormat vform, in ld3r() function in vixl::aarch64::Simulator
Dassembler-aarch64.cc1641 void Assembler::ld3r(const VRegister& vt, in ld3r() function in vixl::aarch64::Assembler
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md2616 void ld3r(const VRegister& vt,
/external/valgrind/none/tests/arm64/
Dmemory.stdout.exp18641 ld3r {v17.2d , v18.2d , v19.2d }, [x5] with x5 = middle_of_block+3, x6=-5
18671 ld3r {v18.1d , v19.1d , v20.1d }, [x5] with x5 = middle_of_block+3, x6=-4
18701 ld3r {v17.4s , v18.4s , v19.4s }, [x5] with x5 = middle_of_block+3, x6=-3
18731 ld3r {v18.2s , v19.2s , v20.2s }, [x5] with x5 = middle_of_block+3, x6=-2
18761 ld3r {v17.8h , v18.8h , v19.8h }, [x5] with x5 = middle_of_block+3, x6=-5
18791 ld3r {v18.4h , v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=-4
18821 ld3r {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+3, x6=-3
18851 ld3r {v18.8b , v19.8b , v20.8b }, [x5] with x5 = middle_of_block+3, x6=-2
18881 ld3r {v17.2d , v18.2d , v19.2d }, [x5], #24 with x5 = middle_of_block+3, x6=-5
18911 ld3r {v18.1d , v19.1d , v20.1d }, [x5], #24 with x5 = middle_of_block+3, x6=-4
[all …]
/external/hyphenation-patterns/de/
Dhyph-de-ch-1901.pat.txt9919 ld3r
Dhyph-de-1996.pat.txt9867 ld3r
Dhyph-de-1901.pat.txt10024 ld3r
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td5078 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen239 aarch64_neon_ld3r, // llvm.aarch64.neon.ld3r
6297 "llvm.aarch64.neon.ld3r",
14237 2, // llvm.aarch64.neon.ld3r

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