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Searched refs:ld4 (Results 1 – 25 of 52) sorted by relevance

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/external/llvm/test/Transforms/EarlyCSE/AArch64/
DldstN.ll5 declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0v4i16(<4 x i1…
7 ; Although the store and the ld4 are using the same pointer, the
8 ; data can not be reused because ld4 accesses multiple elements.
12 …%0 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0v4i16(<4 x…
/external/llvm/test/MC/AArch64/
Dneon-simd-ldst-multi-elem.s435 ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
436 ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
437 ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
438 ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
439 ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
440 ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
441 ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
450 ld4 { v0.16b-v3.16b }, [x0]
451 ld4 { v15.8h-v18.8h }, [x15]
452 ld4 { v31.4s-v2.4s }, [sp]
[all …]
Darm64-simd-ldst.s289 ld4.8b {v4, v5, v6, v7}, [x19]
290 ld4.16b {v4, v5, v6, v7}, [x19]
291 ld4.4h {v4, v5, v6, v7}, [x19]
292 ld4.8h {v4, v5, v6, v7}, [x19]
293 ld4.2s {v4, v5, v6, v7}, [x19]
294 ld4.4s {v4, v5, v6, v7}, [x19]
295 ld4.2d {v4, v5, v6, v7}, [x19]
306 ; CHECK: ld4.8b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x40,0x0c]
307 ; CHECK: ld4.16b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x40,0x4c]
308 ; CHECK: ld4.4h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x40,0x0c]
[all …]
Dneon-simd-ldst-one-elem.s114 ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
115 ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]
116 ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp]
117 ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
275 ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
276 ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7
277 ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16
278 ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
Dneon-simd-post-ldst-multi-elem.s176 ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
177 ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
178 ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
179 ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
180 ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
181 ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
182 ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
/external/libavc/common/armv8/
Dih264_deblk_chroma_av8.s198 ld4 {v0.h, v1.h, v2.h, v3.h}[0], [x0], x1
199 ld4 {v0.h, v1.h, v2.h, v3.h}[1], [x0], x1
200 ld4 {v0.h, v1.h, v2.h, v3.h}[2], [x0], x1
201 ld4 {v0.h, v1.h, v2.h, v3.h}[3], [x0], x1
203 ld4 {v4.h, v5.h, v6.h, v7.h}[0], [x0], x1
204 ld4 {v4.h, v5.h, v6.h, v7.h}[1], [x0], x1
205 ld4 {v4.h, v5.h, v6.h, v7.h}[2], [x0], x1
206 ld4 {v4.h, v5.h, v6.h, v7.h}[3], [x0], x1
479 ld4 {v0.h, v1.h, v2.h, v3.h}[0], [x0], x1
480 ld4 {v0.h, v1.h, v2.h, v3.h}[1], [x0], x1
[all …]
Dih264_iquant_itrans_recon_av8.s137 ld4 {v20.4h - v23.4h}, [x5] // load pu2_iscal_mat[i], i =0..15
138 ld4 {v26.4h - v29.4h}, [x6] // pu2_weigh_mat[i], i =0..15
139 ld4 {v16.4h - v19.4h}, [x0] // pi2_src_tmp[i], i =0..15
330 ld4 {v20.4h - v23.4h}, [x5] // load pu2_iscal_mat[i], i =0..15
331 ld4 {v26.4h - v29.4h}, [x6] // pu2_weigh_mat[i], i =0..15
332 ld4 {v16.4h - v19.4h}, [x0] // pi2_src_tmp[i], i =0..15
Dih264_ihadamard_scaling_av8.s103 ld4 {v0.4h-v3.4h}, [x0] //load x4,x5,x6,x7
/external/llvm/test/CodeGen/AArch64/
Darm64-indexed-vector-ldst.ll1121 ;CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], #64
1122 …%ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(…
1125 ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
1130 ;CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
1131 …%ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(…
1134 ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
1137 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(i8*)
1142 ;CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], #32
1143 …%ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4.v8i8.p0i8(i8* %…
1146 ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
[all …]
Darm64-neon-vector-list-spill.ll49 ; CHECK: ld4 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}]
53 …%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16…
109 ; CHECK: ld4 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}…
113 …%vld = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(…
129 declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16(i16*)
132 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(i8*)
Darm64-ld1.ll29 ; CHECK: ld4.8b { v0, v1, v2, v3 }, [x0]
31 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4.v8i8.p0i8(i8* %A)
37 declare %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4.v8i8.p0i8(i8*) nounwind readonly
64 ; CHECK: ld4.16b { v0, v1, v2, v3 }, [x0]
66 %tmp2 = call %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4.v16i8.p0i8(i8* %A)
72 declare %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4.v16i8.p0i8(i8*) nounwind readonly
99 ; CHECK: ld4.4h { v0, v1, v2, v3 }, [x0]
101 %tmp2 = call %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4.v4i16.p0i16(i16* %A)
107 declare %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4.v4i16.p0i16(i16*) nounwind readonly
134 ; CHECK: ld4.8h { v0, v1, v2, v3 }, [x0]
[all …]
Daarch64-interleaved-accesses.ll30 ; NEON: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
32 ; NONEON-NOT: ld4
107 ; NEON: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
109 ; NONEON-NOT: ld4
187 ; NEON: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
189 ; NONEON-NOT: ld4
Dfp16-vector-load-store.ll104 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v4f16(<4 …
110 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v8f16(<8 …
136 ; CHECK: ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]
138 …%0 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v…
190 ; CHECK: ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x0]
192 …%0 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v…
321 ; CHECK: ld4 { v0.h, v1.h, v2.h, v3.h }[2], [x0]
375 ; CHECK: ld4 { v0.h, v1.h, v2.h, v3.h }[2], [x0]
Darm64-misched-basic-A53.ll190 …%0 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i8(i8* nul…
204 declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i8(i8*)
/external/libunwind/tests/
Dia64-test-rbs-asm.S149 ld4 loc##n = [in1], 4;; \
152 (p8) ld4.s loc##n = [r0]
155 ld4 r16 = [in1], 4;; \
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1295 # CHECK: ld4.8b { v1, v2, v3, v4 }, [x1]
1296 # CHECK: ld4.16b { v5, v6, v7, v8 }, [x2]
1297 # CHECK: ld4.2s { v10, v11, v12, v13 }, [x0]
1312 # CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], x4
1313 # CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], x5
1314 # CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], x6
1315 # CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], x7
1322 # CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], #4
1323 # CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], #32
1324 # CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], #8
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dspill-q.ll28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
71 %tmp2 = fadd <4 x float> %tmp1, %ld4
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dthumb2-spill-q.ll28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
71 %tmp2 = fadd <4 x float> %tmp1, %ld4
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dbswap.ll123 %ld4 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @src32, i32 0, i64 4), align 2
131 %bswap4 = call i32 @llvm.bswap.i32(i32 %ld4)
157 …%ld4 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @src16, i16 0, i64 4), align…
165 %bswap4 = call i16 @llvm.bswap.i16(i16 %ld4)
200 …%ld4 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @src16, i16 0, i64 4), ali…
216 %bswap4 = call i16 @llvm.bswap.i16(i16 %ld4)
Dctpop.ll111 %ld4 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @src32, i32 0, i64 4), align 2
119 %ctpop4 = call i32 @llvm.ctpop.i32(i32 %ld4)
145 …%ld4 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @src16, i16 0, i64 4), align…
153 %ctpop4 = call i16 @llvm.ctpop.i16(i16 %ld4)
188 …%ld4 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @src16, i16 0, i64 4), ali…
204 %ctpop4 = call i16 @llvm.ctpop.i16(i16 %ld4)
246 %ld4 = load i8, i8* getelementptr inbounds ([32 x i8], [32 x i8]* @src8, i8 0, i64 4), align 1
262 %ctpop4 = call i8 @llvm.ctpop.i8(i8 %ld4)
307 %ld4 = load i8, i8* getelementptr inbounds ([32 x i8], [32 x i8]* @src8, i8 0, i64 4), align 1
339 %ctpop4 = call i8 @llvm.ctpop.i8(i8 %ld4)
/external/llvm/test/CodeGen/ARM/
Dspill-q.ll28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
71 %tmp2 = fadd <4 x float> %tmp1, %ld4
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-spill-q.ll28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
71 %tmp2 = fadd <4 x float> %tmp1, %ld4
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1077 __ ld4(v3.V16B(), v4.V16B(), v5.V16B(), v6.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1078 __ ld4(v2.V16B(), in GenerateTestSequenceNEON() local
1083 __ ld4(v5.V16B(), in GenerateTestSequenceNEON() local
1088 __ ld4(v18.V2D(), v19.V2D(), v20.V2D(), v21.V2D(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1089 __ ld4(v4.V2D(), v5.V2D(), v6.V2D(), v7.V2D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
1090 __ ld4(v29.V2D(), in GenerateTestSequenceNEON() local
1095 __ ld4(v27.V2S(), v28.V2S(), v29.V2S(), v30.V2S(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1096 __ ld4(v24.V2S(), in GenerateTestSequenceNEON() local
1101 __ ld4(v4.V2S(), v5.V2S(), v6.V2S(), v7.V2S(), MemOperand(x1, 32, PostIndex)); in GenerateTestSequenceNEON() local
1102 __ ld4(v16.V4H(), v17.V4H(), v18.V4H(), v19.V4H(), MemOperand(x0)); in GenerateTestSequenceNEON() local
[all …]
/external/vixl/test/test-trace-reference/
Dlog-disasm943 0x~~~~~~~~~~~~~~~~ 4c400003 ld4 {v3.16b, v4.16b, v5.16b, v6.16b}, [x0]
944 0x~~~~~~~~~~~~~~~~ 4cc20022 ld4 {v2.16b, v3.16b, v4.16b, v5.16b}, [x1], x2
945 0x~~~~~~~~~~~~~~~~ 4cdf0025 ld4 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
946 0x~~~~~~~~~~~~~~~~ 4c400c12 ld4 {v18.2d, v19.2d, v20.2d, v21.2d}, [x0]
947 0x~~~~~~~~~~~~~~~~ 4cc20c24 ld4 {v4.2d, v5.2d, v6.2d, v7.2d}, [x1], x2
948 0x~~~~~~~~~~~~~~~~ 4cdf0c3d ld4 {v29.2d, v30.2d, v31.2d, v0.2d}, [x1], #64
949 0x~~~~~~~~~~~~~~~~ 0c40081b ld4 {v27.2s, v28.2s, v29.2s, v30.2s}, [x0]
950 0x~~~~~~~~~~~~~~~~ 0cc20838 ld4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
951 0x~~~~~~~~~~~~~~~~ 0cdf0824 ld4 {v4.2s, v5.2s, v6.2s, v7.2s}, [x1], #32
952 0x~~~~~~~~~~~~~~~~ 0c400410 ld4 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
[all …]
Dlog-disasm-colour943 0x~~~~~~~~~~~~~~~~ 4c400003 ld4 {v3.16b, v4.16b, v5.16b, v6.16b}, [x0]
944 0x~~~~~~~~~~~~~~~~ 4cc20022 ld4 {v2.16b, v3.16b, v4.16b, v5.16b}, [x1], x2
945 0x~~~~~~~~~~~~~~~~ 4cdf0025 ld4 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
946 0x~~~~~~~~~~~~~~~~ 4c400c12 ld4 {v18.2d, v19.2d, v20.2d, v21.2d}, [x0]
947 0x~~~~~~~~~~~~~~~~ 4cc20c24 ld4 {v4.2d, v5.2d, v6.2d, v7.2d}, [x1], x2
948 0x~~~~~~~~~~~~~~~~ 4cdf0c3d ld4 {v29.2d, v30.2d, v31.2d, v0.2d}, [x1], #64
949 0x~~~~~~~~~~~~~~~~ 0c40081b ld4 {v27.2s, v28.2s, v29.2s, v30.2s}, [x0]
950 0x~~~~~~~~~~~~~~~~ 0cc20838 ld4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
951 0x~~~~~~~~~~~~~~~~ 0cdf0824 ld4 {v4.2s, v5.2s, v6.2s, v7.2s}, [x1], #32
952 0x~~~~~~~~~~~~~~~~ 0c400410 ld4 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
[all …]

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