/external/llvm/test/CodeGen/ARM/ |
D | ldaex-stlex.ll | 7 ; CHECK: ldaexd 10 %ldaexd = tail call %0 @llvm.arm.ldaexd(i8* %p) 11 %0 = extractvalue %0 %ldaexd, 1 12 %1 = extractvalue %0 %ldaexd, 0 31 declare %0 @llvm.arm.ldaexd(i8*) nounwind readonly
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D | atomic-ops-v8.ll | 185 ; CHECK: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] 281 ; CHECK: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] 566 ; CHECK: ldaexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] 667 ; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] 893 ; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] 1006 ; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] 1278 ; CHECK: ldaexd r0, r1, [r[[ADDR]]]
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/external/llvm/test/MC/ARM/ |
D | load-store-acquire-release-v8.s | 6 ldaexd r6, r7, [r8] 11 @ CHECK: ldaexd r6, r7, [r8] @ encoding: [0x9f,0x6e,0xb8,0xe1]
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D | load-store-acquire-release-v8-thumb.s | 6 ldaexd r6, r7, [r8] 11 @ CHECK: ldaexd r6, r7, [r8] @ encoding: [0xd8,0xe8,0xff,0x67]
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D | thumbv8m.s | 127 ldaexd r0, r1, [r2] label
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/external/llvm/test/MC/Disassembler/ARM/ |
D | load-store-acquire-release-v8.txt | 9 # CHECK: ldaexd r8, r9, [sp] @ encoding: [0x9f,0x8e,0xbd,0xe1]
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D | load-store-acquire-release-v8-thumb.txt | 10 # CHECK: ldaexd r6, r7, [r8] @ encoding: [0xd8,0xe8,0xff,0x67]
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/external/llvm/test/Transforms/AtomicExpand/ARM/ |
D | atomic-expansion-v8.ll | 63 ; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldaexd(i8* [[PTR8]])
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/external/valgrind/none/tests/arm/ |
D | v8memory_t.stdout.exp | 142 ldaexd r2, r3, [r10] with r10 = middle_of_block 266 mov r4, r2 ; mov r5, r3 ; ldaexd r2, r3, [r10] ; mov r2, r4 ; mov r3, r5 ; stlexd r9, r2, r3, [r10]…
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D | v8memory_a.stdout.exp | 142 ldaexd r2, r3, [r10] with r10 = middle_of_block 266 mov r4, r2 ; mov r5, r3 ; ldaexd r2, r3, [r10] ; mov r2, r4 ; mov r3, r5 ; stlexd r9, r2, r3, [r10]…
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 2239 void ldaexd(Condition cond, 2243 void ldaexd(Register rt, Register rt2, const MemOperand& operand) { in ldaexd() function 2244 ldaexd(al, rt, rt2, operand); in ldaexd()
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D | disasm-aarch32.h | 650 void ldaexd(Condition cond,
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D | assembler-aarch32.cc | 4315 void Assembler::ldaexd(Condition cond, in ldaexd() function in vixl::aarch32::Assembler 4343 Delegate(kLdaexd, &Assembler::ldaexd, cond, rt, rt2, operand); in ldaexd()
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D | disasm-aarch32.cc | 1593 void Disassembler::ldaexd(Condition cond, in ldaexd() function in vixl::aarch32::Disassembler 10557 ldaexd(CurrentCond(), in DecodeT32() 60413 ldaexd(condition, in DecodeA32()
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D | macro-assembler-aarch32.h | 1965 ldaexd(cond, rt, rt2, operand); in Ldaexd()
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 3339 "ldaexd", "\t$Rt, $Rt2, $addr", "",
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D | ARMInstrInfo.td | 4709 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
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/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
D | Intrinsics.gen | 542 arm_ldaexd, // llvm.arm.ldaexd 6600 "llvm.arm.ldaexd", 14540 3, // llvm.arm.ldaexd
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/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
D | Intrinsics.gen | 537 arm_ldaexd, // llvm.arm.ldaexd 6561 "llvm.arm.ldaexd", 14446 3, // llvm.arm.ldaexd
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/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
D | Intrinsics.gen | 542 arm_ldaexd, // llvm.arm.ldaexd 6600 "llvm.arm.ldaexd", 14540 3, // llvm.arm.ldaexd
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/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
D | Intrinsics.gen | 542 arm_ldaexd, // llvm.arm.ldaexd 6600 "llvm.arm.ldaexd", 14540 3, // llvm.arm.ldaexd
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