Home
last modified time | relevance | path

Searched refs:ldaexd (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/CodeGen/ARM/
Dldaex-stlex.ll7 ; CHECK: ldaexd
10 %ldaexd = tail call %0 @llvm.arm.ldaexd(i8* %p)
11 %0 = extractvalue %0 %ldaexd, 1
12 %1 = extractvalue %0 %ldaexd, 0
31 declare %0 @llvm.arm.ldaexd(i8*) nounwind readonly
Datomic-ops-v8.ll185 ; CHECK: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
281 ; CHECK: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
566 ; CHECK: ldaexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
667 ; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
893 ; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
1006 ; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
1278 ; CHECK: ldaexd r0, r1, [r[[ADDR]]]
/external/llvm/test/MC/ARM/
Dload-store-acquire-release-v8.s6 ldaexd r6, r7, [r8]
11 @ CHECK: ldaexd r6, r7, [r8] @ encoding: [0x9f,0x6e,0xb8,0xe1]
Dload-store-acquire-release-v8-thumb.s6 ldaexd r6, r7, [r8]
11 @ CHECK: ldaexd r6, r7, [r8] @ encoding: [0xd8,0xe8,0xff,0x67]
Dthumbv8m.s127 ldaexd r0, r1, [r2] label
/external/llvm/test/MC/Disassembler/ARM/
Dload-store-acquire-release-v8.txt9 # CHECK: ldaexd r8, r9, [sp] @ encoding: [0x9f,0x8e,0xbd,0xe1]
Dload-store-acquire-release-v8-thumb.txt10 # CHECK: ldaexd r6, r7, [r8] @ encoding: [0xd8,0xe8,0xff,0x67]
/external/llvm/test/Transforms/AtomicExpand/ARM/
Datomic-expansion-v8.ll63 ; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldaexd(i8* [[PTR8]])
/external/valgrind/none/tests/arm/
Dv8memory_t.stdout.exp142 ldaexd r2, r3, [r10] with r10 = middle_of_block
266 mov r4, r2 ; mov r5, r3 ; ldaexd r2, r3, [r10] ; mov r2, r4 ; mov r3, r5 ; stlexd r9, r2, r3, [r10]…
Dv8memory_a.stdout.exp142 ldaexd r2, r3, [r10] with r10 = middle_of_block
266 mov r4, r2 ; mov r5, r3 ; ldaexd r2, r3, [r10] ; mov r2, r4 ; mov r3, r5 ; stlexd r9, r2, r3, [r10]…
/external/vixl/src/aarch32/
Dassembler-aarch32.h2239 void ldaexd(Condition cond,
2243 void ldaexd(Register rt, Register rt2, const MemOperand& operand) { in ldaexd() function
2244 ldaexd(al, rt, rt2, operand); in ldaexd()
Ddisasm-aarch32.h650 void ldaexd(Condition cond,
Dassembler-aarch32.cc4315 void Assembler::ldaexd(Condition cond, in ldaexd() function in vixl::aarch32::Assembler
4343 Delegate(kLdaexd, &Assembler::ldaexd, cond, rt, rt2, operand); in ldaexd()
Ddisasm-aarch32.cc1593 void Disassembler::ldaexd(Condition cond, in ldaexd() function in vixl::aarch32::Disassembler
10557 ldaexd(CurrentCond(), in DecodeT32()
60413 ldaexd(condition, in DecodeA32()
Dmacro-assembler-aarch32.h1965 ldaexd(cond, rt, rt2, operand); in Ldaexd()
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td3339 "ldaexd", "\t$Rt, $Rt2, $addr", "",
DARMInstrInfo.td4709 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen542 arm_ldaexd, // llvm.arm.ldaexd
6600 "llvm.arm.ldaexd",
14540 3, // llvm.arm.ldaexd
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen537 arm_ldaexd, // llvm.arm.ldaexd
6561 "llvm.arm.ldaexd",
14446 3, // llvm.arm.ldaexd
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen542 arm_ldaexd, // llvm.arm.ldaexd
6600 "llvm.arm.ldaexd",
14540 3, // llvm.arm.ldaexd
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen542 arm_ldaexd, // llvm.arm.ldaexd
6600 "llvm.arm.ldaexd",
14540 3, // llvm.arm.ldaexd