| /external/llvm/test/CodeGen/PowerPC/ |
| D | hidden-vis-2.ll | 5 ; CHECK: lwz r2, lo16(L_x$non_lazy_ptr)(r2)
6 ; CHECK: lwz r3, lo16(L_y$non_lazy_ptr)(r3)
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| D | indirectbr.ll | 62 ; PIC: li r[[R1:[0-9]+]], lo16(Ltmp0-L0$pb)
66 ; STATIC: li r[[R0:[0-9]+]], lo16(Ltmp0)
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| D | hello-reloc.s | 28 la r3, lo16(L_.str-L0$pb)(r2)
47 lwzu r12, lo16(L_puts$lazy_ptr-L_puts$stub$tmp)(r11)
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| /external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
| D | available-externally.ll | 43 ; PIC: lwzu r12,lo16(L_exact_log2$lazy_ptr-L_exact_log2$stub$tmp)(r11)
59 ; DYNAMIC: lwzu r12,lo16(L_exact_log2$lazy_ptr)(r11)
|
| D | indirectbr.ll | 51 ; PIC: li r[[R1:[0-9]+]], lo16(Ltmp0-L0$pb)
54 ; STATIC: li r[[R0:[0-9]+]], lo16(Ltmp0)
|
| D | stubs.ll | 14 ; CHECK: lwzu r12,lo16(___floatditf$lazy_ptr)(r11)
|
| /external/llvm/lib/Target/PowerPC/ |
| D | README.txt | 73 lfd f0, lo16(.CPI_X_0)(r2)
75 lfd f2, lo16(.CPI_X_1)(r2)
78 lfd f1, lo16(.CPI_X_2)(r2)
80 lfd f2, lo16(.CPI_X_3)(r2)
99 lfs f0, lo16(LCPI1_0)(r2)
102 lfs f2, lo16(LCPI1_2)(r3)
103 lfs f3, lo16(LCPI1_1)(r2)
191 la r2, lo16(_a)(r2)
200 lbz r2, lo16(_a+3)(r2)
363 lfs f0, lo16(.CPI_foo_0-"L00000$pb")(r2)
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| D | README_ALTIVEC.txt | 130 lfs f0, lo16(LCPI1_0)(r3)
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinInstrInfo.td | 304 (EXTRACT_SUBREG (LOAD32p_8z P:$ptr), lo16)>;
306 (EXTRACT_SUBREG (LOAD32p_8z P:$ptr), lo16)>;
316 lo16)>;
319 lo16)>;
326 (EXTRACT_SUBREG (LOAD32p_8s P:$ptr), lo16)>;
334 lo16)>;
471 lo16), PI:$ptr)>;
480 lo16),
519 lo16)),
520 lo16)>;
[all …]
|
| D | BlackfinRegisterInfo.td | 19 def lo16 : SubRegIndex;
68 let SubRegIndices = [hi16, lo16];
226 let SubRegClasses = [(D16L lo16), (D16H hi16)];
230 let SubRegClasses = [(P16L lo16), (P16H hi16)];
234 let SubRegClasses = [(DP16L lo16), (DP16H hi16)];
|
| D | BlackfinRegisterInfo.cpp | 148 TII.get(BF::LOAD16i), getSubReg(Reg, BF::lo16)) in loadConstant()
|
| /external/python/cpython2/Modules/_ctypes/libffi_osx/powerpc/ |
| D | ppc64-darwin_closure.S | 368 lgu r12,lo16(L_ffi_closure_helper_DARWIN$lazy_ptr - LO$ffi_closure_helper_DARWIN)(r11)
389 lgu r12,lo16(L_ffi64_struct_to_reg_form$lazy_ptr - LO$ffi64_struct_to_reg_form)(r11)
405 lgu r12,lo16(L_ffi64_data_size$lazy_ptr - LO$ffi64_data_size)(r11)
|
| D | ppc-darwin_closure.S | 298 lgu r12,lo16(L_ffi_closure_helper_DARWIN$lazy_ptr - LO$ffi_closure_helper_DARWIN)(r11)
|
| D | ppc-darwin.S | 355 lgu r12,lo16(L_ffi64_struct_to_ram_form$lazy_ptr - LO$ffi64_struct_to_ram_form)(r11)
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | README.txt | 160 lfd f0, lo16(.CPI_X_0)(r2)
162 lfd f2, lo16(.CPI_X_1)(r2)
165 lfd f1, lo16(.CPI_X_2)(r2)
167 lfd f2, lo16(.CPI_X_3)(r2)
186 lfs f0, lo16(LCPI1_0)(r2)
189 lfs f2, lo16(LCPI1_2)(r3)
190 lfs f3, lo16(LCPI1_1)(r2)
362 la r2, lo16(_a)(r2)
371 lbz r2, lo16(_a+3)(r2)
637 lfs f0, lo16(.CPI_foo_0-"L00000$pb")(r2)
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| D | README_ALTIVEC.txt | 130 lfs f0, lo16(LCPI1_0)(r3)
|
| /external/valgrind/VEX/priv/ |
| D | host_arm_defs.c | 2938 UInt lo16 = imm32 & 0xFFFF; in imm32_to_ireg() local
2940 instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD, in imm32_to_ireg()
2941 (lo16 >> 8) & 0xF, (lo16 >> 4) & 0xF, in imm32_to_ireg()
2942 lo16 & 0xF); in imm32_to_ireg()
2999 UInt lo16 = imm32 & 0xFFFF; in imm32_to_ireg_EXACTLY2() local
3002 instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD, in imm32_to_ireg_EXACTLY2()
3003 (lo16 >> 8) & 0xF, (lo16 >> 4) & 0xF, in imm32_to_ireg_EXACTLY2()
3004 lo16 & 0xF); in imm32_to_ireg_EXACTLY2()
3022 UInt lo16 = imm32 & 0xFFFF; in is_imm32_to_ireg_EXACTLY2() local
3025 i0 = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD, in is_imm32_to_ireg_EXACTLY2()
[all …]
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| D | host_x86_isel.c | 1064 HReg lo16 = newVRegI(env); in iselIntExpr_R_wrk() local
1068 addInstr(env, mk_iMOVsd_RR(lo16s, lo16)); in iselIntExpr_R_wrk()
1070 addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(0xFFFF), lo16)); in iselIntExpr_R_wrk()
1071 addInstr(env, X86Instr_Alu32R(Xalu_OR, X86RMI_Reg(lo16), hi16)); in iselIntExpr_R_wrk()
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| D | host_amd64_isel.c | 1289 HReg lo16 = newVRegI(env); in iselIntExpr_R_wrk() local
1293 addInstr(env, mk_iMOVsd_RR(lo16s, lo16)); in iselIntExpr_R_wrk()
1296 Aalu_AND, AMD64RMI_Imm(0xFFFF), lo16)); in iselIntExpr_R_wrk()
1298 Aalu_OR, AMD64RMI_Reg(lo16), hi16)); in iselIntExpr_R_wrk()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUOperands.td | 149 def lo16 : PatLeaf<(imm), [{
150 // lo16 predicate - returns true if the immediate has all zeros in the
|