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Searched refs:lsrs (Results 1 – 25 of 61) sorted by relevance

123

/external/llvm/test/MC/ARM/
Dbasic-thumb-instructions.s377 lsrs r1, r3, #1
378 lsrs r1, r3, #32
379 lsrs r4, #20
380 lsrs r4, r4, #20
381 lsrs r2, r4, #20
383 @ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08]
384 @ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08]
385 @ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
386 @ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
387 @ CHECK: lsrs r2, r4, #20 @ encoding: [0x22,0x0d]
[all …]
Dthumb_rewrites.s74 lsrs r0, r0, r1
75 @ CHECK: lsrs r0, r1 @ encoding: [0xc8,0x40]
/external/llvm/test/CodeGen/ARM/Windows/
Dvla.ll18 ; CHECK-SMALL-CODE: lsrs r4, [[R4]], #2
24 ; CHECK-LARGE-CODE: lsrs r4, [[R4]], #2
Dalloca.ll21 ; CHECK: lsrs r4, [[R0]], #2
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-shifter.ll59 ; A8: lsrs r1, r2
63 ; SWIFT-NOT: lsrs
99 ; SWIFT: lsrs
Dbfi.ll22 ; CHECK: lsrs r1, r1, #7
33 ; CHECK: lsrs {{.*}}, #7
Dthumb2-lsr.ll5 ; CHECK: lsrs r0, r0, #13
Dthumb2-lsr2.ll5 ; CHECK: lsrs r0, r1
Dthumb2-lsr3.ll5 ; CHECK: lsrs.w r1, r1, #1
Dfloat-intrinsics-float.ll119 ; NONE: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
121 ; SP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
123 ; VFP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
Dfloat-intrinsics-double.ll115 ; SP: lsrs r2, r3, #31
126 ; SOFT: lsrs [[REG:r[0-9]+]], r3, #31
128 ; VFP: lsrs [[REG:r[0-9]+]], r3, #31
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dbfi.ll22 ; CHECK: lsrs r1, r1, #7
33 ; CHECK: lsrs {{.*}}, #7
Dthumb2-lsr.ll5 ; CHECK: lsrs r0, r0, #13
Dthumb2-lsr2.ll5 ; CHECK: lsrs r0, r1
Dthumb2-lsr3.ll5 ; CHECK: lsrs.w r1, r1, #1
Dthumb2-sxt_rot.ll22 ; CHECK: lsrs r0, r0, #8
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-thumb-instructions.s334 lsrs r1, r3, #1
335 lsrs r1, r3, #32
337 @ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08]
338 @ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08]
344 lsrs r2, r6
346 @ CHECK: lsrs r2, r6 @ encoding: [0xf2,0x40]
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/
Dispositive.ll6 ; CHECK: lsrs r0, r0, #31
/external/llvm/test/CodeGen/Thumb/
Dispositive.ll6 ; CHECK: lsrs r0, r0, #31
/external/llvm/test/CodeGen/ARM/
Dlong_shift.ll6 ; CHECK-LE: lsrs r3, r3, #1
10 ; CHECK-BE: lsrs r2, r2, #1
Dthumb2-size-opt.ll71 ; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}]
80 ; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
/external/compiler-rt/lib/builtins/arm/
Dclzsi2.S51 lsrs r2, r0, shift; \
Dclzdi2.S72 lsrs r2, r0, shift; \
/external/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt255 # CHECK: lsrs r1, r3, #1
256 # CHECK: lsrs r1, r3, #32
265 # CHECK: lsrs r2, r6
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dthumb1.txt240 # CHECK: lsrs r1, r3, #1
241 # CHECK: lsrs r1, r3, #32
250 # CHECK: lsrs r2, r6

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