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/external/valgrind/none/tests/mips64/
Dfpu_load_store.stdout.exp-BE772 lwc1 :: offset: 0x0, out: 0x0
773 lwc1 :: offset: 0x4, out: 0x0
774 lwc1 :: offset: 0x8, out: 0x9823b6e
775 lwc1 :: offset: 0xc, out: 0xd4326d9
776 lwc1 :: offset: 0x10, out: 0x130476dc
777 lwc1 :: offset: 0x14, out: 0x17c56b6b
778 lwc1 :: offset: 0x18, out: 0x1a864db2
779 lwc1 :: offset: 0x1c, out: 0x1e475005
780 lwc1 :: offset: 0x20, out: 0x2608edb8
781 lwc1 :: offset: 0x24, out: 0x22c9f00f
[all …]
Dfpu_load_store.stdout.exp-LE772 lwc1 :: offset: 0x0, out: 0x0
773 lwc1 :: offset: 0x4, out: 0x0
774 lwc1 :: offset: 0x8, out: 0x9823b6e
775 lwc1 :: offset: 0xc, out: 0xd4326d9
776 lwc1 :: offset: 0x10, out: 0x130476dc
777 lwc1 :: offset: 0x14, out: 0x17c56b6b
778 lwc1 :: offset: 0x18, out: 0x1a864db2
779 lwc1 :: offset: 0x1c, out: 0x1e475005
780 lwc1 :: offset: 0x20, out: 0x2608edb8
781 lwc1 :: offset: 0x24, out: 0x22c9f00f
[all …]
/external/valgrind/none/tests/mips32/
Dvfp.stdout.exp-mips32-BE30 lwc1 $f0, 0($t1) :: ft 0x4095a266
31 lwc1 $f0, 4($t1) :: ft 0x66666666
32 lwc1 $f0, 8($t1) :: ft 0xbff00000
33 lwc1 $f0, 12($t1) :: ft 0x0
34 lwc1 $f0, 16($t1) :: ft 0x3ff00000
35 lwc1 $f0, 20($t1) :: ft 0x0
36 lwc1 $f0, 24($t1) :: ft 0x252a2e2b
37 lwc1 $f0, 28($t1) :: ft 0x262d2d2a
38 lwc1 $f0, 32($t1) :: ft 0xffffffff
39 lwc1 $f0, 36($t1) :: ft 0xffffffff
[all …]
Dvfp.stdout.exp-mips32-LE30 lwc1 $f0, 0($t1) :: ft 0x4095a266
31 lwc1 $f0, 4($t1) :: ft 0x66666666
32 lwc1 $f0, 8($t1) :: ft 0xbff00000
33 lwc1 $f0, 12($t1) :: ft 0x0
34 lwc1 $f0, 16($t1) :: ft 0x3ff00000
35 lwc1 $f0, 20($t1) :: ft 0x0
36 lwc1 $f0, 24($t1) :: ft 0x252a2e2b
37 lwc1 $f0, 28($t1) :: ft 0x262d2d2a
38 lwc1 $f0, 32($t1) :: ft 0xffffffff
39 lwc1 $f0, 36($t1) :: ft 0xffffffff
[all …]
Dvfp.stdout.exp-mips32r2-BE30 lwc1 $f0, 0($t1) :: ft 0x4095a266
31 lwc1 $f0, 4($t1) :: ft 0x66666666
32 lwc1 $f0, 8($t1) :: ft 0xbff00000
33 lwc1 $f0, 12($t1) :: ft 0x0
34 lwc1 $f0, 16($t1) :: ft 0x3ff00000
35 lwc1 $f0, 20($t1) :: ft 0x0
36 lwc1 $f0, 24($t1) :: ft 0x252a2e2b
37 lwc1 $f0, 28($t1) :: ft 0x262d2d2a
38 lwc1 $f0, 32($t1) :: ft 0xffffffff
39 lwc1 $f0, 36($t1) :: ft 0xffffffff
[all …]
Dvfp.stdout.exp-mips32r2-LE30 lwc1 $f0, 0($t1) :: ft 0x4095a266
31 lwc1 $f0, 4($t1) :: ft 0x66666666
32 lwc1 $f0, 8($t1) :: ft 0xbff00000
33 lwc1 $f0, 12($t1) :: ft 0x0
34 lwc1 $f0, 16($t1) :: ft 0x3ff00000
35 lwc1 $f0, 20($t1) :: ft 0x0
36 lwc1 $f0, 24($t1) :: ft 0x252a2e2b
37 lwc1 $f0, 28($t1) :: ft 0x262d2d2a
38 lwc1 $f0, 32($t1) :: ft 0xffffffff
39 lwc1 $f0, 36($t1) :: ft 0xffffffff
[all …]
Dvfp.stdout.exp-mips32r2-fpu_64-LE30 lwc1 $f0, 0($t1) :: ft 0x4095a266
31 lwc1 $f0, 4($t1) :: ft 0x66666666
32 lwc1 $f0, 8($t1) :: ft 0xbff00000
33 lwc1 $f0, 12($t1) :: ft 0x0
34 lwc1 $f0, 16($t1) :: ft 0x3ff00000
35 lwc1 $f0, 20($t1) :: ft 0x0
36 lwc1 $f0, 24($t1) :: ft 0x252a2e2b
37 lwc1 $f0, 28($t1) :: ft 0x262d2d2a
38 lwc1 $f0, 32($t1) :: ft 0xffffffff
39 lwc1 $f0, 36($t1) :: ft 0xffffffff
[all …]
Dvfp.stdout.exp-mips32r2-fpu_64-BE30 lwc1 $f0, 0($t1) :: ft 0x4095a266
31 lwc1 $f0, 4($t1) :: ft 0x66666666
32 lwc1 $f0, 8($t1) :: ft 0xbff00000
33 lwc1 $f0, 12($t1) :: ft 0x0
34 lwc1 $f0, 16($t1) :: ft 0x3ff00000
35 lwc1 $f0, 20($t1) :: ft 0x0
36 lwc1 $f0, 24($t1) :: ft 0x252a2e2b
37 lwc1 $f0, 28($t1) :: ft 0x262d2d2a
38 lwc1 $f0, 32($t1) :: ft 0xffffffff
39 lwc1 $f0, 36($t1) :: ft 0xffffffff
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Do32_cc.ll18 ; CHECK: lwc1 $f12, %lo
19 ; CHECK: lwc1 $f14, %lo
29 ; CHECK: lwc1 $f12, %lo
41 ; CHECK: lwc1 $f14, %lo
89 ; CHECK: lwc1 $f12, %lo
153 ; CHECK: lwc1 $f12, %lo
154 ; CHECK: lwc1 $f14, %lo
166 ; CHECK: lwc1 $f12, %lo
181 ; CHECK: lwc1 $f14, %lo
192 ; CHECK: lwc1 $f12, %lo
[all …]
Dmips64fpldst.ll13 ; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]])
16 ; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]])
D2009-11-16-CstPoolLoad.ll8 ; CHECK: lwc1 $f0, %lo($CPI0_0)($2)
/external/llvm/test/CodeGen/Mips/
D2009-11-16-CstPoolLoad.ll11 ; PIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]])
13 ; STATIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]])
15 ; PIC-N32: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]])
17 ; STATIC-N32: lwc1 $f0, %lo($CPI0_0)($[[R0]])
19 ; PIC-N64: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]])
21 ; STATIC-N64: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]])
Dfastcc.ll178 ; CHECK: lwc1 $f19
179 ; CHECK: lwc1 $f18
180 ; CHECK: lwc1 $f17
181 ; CHECK: lwc1 $f16
182 ; CHECK: lwc1 $f15
183 ; CHECK: lwc1 $f14
184 ; CHECK: lwc1 $f13
185 ; CHECK: lwc1 $f12
186 ; CHECK: lwc1 $f11
187 ; CHECK: lwc1 $f10
[all …]
Do32_cc.ll20 ; ALL-DAG: lwc1 $f12, %lo
21 ; ALL-DAG: lwc1 $f14, %lo
32 ; ALL-DAG: lwc1 $f12, %lo
45 ; ALL-DAG: lwc1 $f14, %lo
97 ; ALL-DAG: lwc1 $f12, %lo
175 ; ALL-DAG: lwc1 $f12, %lo
176 ; ALL-DAG: lwc1 $f14, %lo
189 ; ALL-DAG: lwc1 $f12, %lo
205 ; ALL-DAG: lwc1 $f14, %lo
217 ; ALL-DAG: lwc1 $f12, %lo
[all …]
Dfp-indexed-ls.ll28 ; MIPS32R1: lwc1 $f0, 0($[[T3]])
35 ; MIPS32R6: lwc1 $f0, 0($[[T3]])
44 ; MIPS64R6: lwc1 $f0, 0($[[T3]])
112 ; MIPS32R1-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
116 ; MIPS32R2: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
119 ; MIPS32R6-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
123 ; MIPS4: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
126 ; MIPS64R6-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
Dreturn-vector.ll62 ; CHECK: lwc1 $[[R0:[a-z0-9]+]], 28($sp)
63 ; CHECK: lwc1 $[[R1:[a-z0-9]+]], 24($sp)
64 ; CHECK: lwc1 $[[R3:[a-z0-9]+]], 20($sp)
65 ; CHECK: lwc1 $[[R4:[a-z0-9]+]], 16($sp)
131 ; CHECK-NOT: lwc1
182 ; CHECK-DAG: lwc1 $[[R0:[a-z0-9]+]], 16($sp)
Dmicromips-lwc1-swc1.ll20 ; MM32: lwc1 $f0, 0($[[R3]])
26 ; MM64: lwc1 $f0, 0($[[R3]])
Dmips64fpldst.ll17 ; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]])
20 ; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]])
Dno-odd-spreg.ll32 ; ODDSPREG-NOT: lwc1
37 ; NOODDSPREG: lwc1 $[[T1:f[0-9]*[02468]]],
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dfpcmpa.ll21 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
22 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
42 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
43 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
62 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
63 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
83 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
84 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
103 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
104 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
[all …]
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dmips-address-mode-opt.ll21 ; MIPS32: lwc1 $f0,16(a0)
32 ; MIPS32 lwc1 $f0,-16(a0)
44 ; MIPS32 lwc1 $f0,8(a0)
Dfp.load_store.ll34 ; MIPS32: lwc1 $f{{.*}},0{{.*}}
36 ; MIPS32O2: lwc1 $f{{.*}},0{{.*}}
98 ; MIPS32: lwc1 $f{{.*}},{{.*}}
102 ; MIPS32O2: lwc1 $f{{.*}},{{.*}}
Dfp_const_pool.ll35 ; MIPS32: lwc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$float$80000000
70 ; MIPS32: lwc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$float$7fc00000
72 ; MIPS32: lwc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$float$7fc00000
74 ; MIPS32: lwc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$float$ffc00000
76 ; MIPS32: lwc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$float$ffc00000
/external/llvm/test/CodeGen/Mips/cconv/
Dreturn-hard-float.ll33 ; O32-DAG: lwc1 $f0, %lo(float)([[R1]])
35 ; N32-DAG: lwc1 $f0, %lo(float)([[R1]])
37 ; N64-DAG: lwc1 $f0, 0([[R1]])
Darguments-hard-float.ll134 ; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 16($sp)
137 ; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 20($sp)
140 ; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 24($sp)
143 ; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 28($sp)
148 ; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 32($sp)
150 ; NEW-DAG: lwc1 [[F1:\$f[0-9]+]], 0($sp)

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