Searched refs:masking (Results 1 – 25 of 57) sorted by relevance
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| /external/llvm/test/MC/Mips/ |
| D | nacl-mask.s | 4 # This test tests that address-masking sandboxing is added when given assembly
8 # Test that address-masking sandboxing is added before indirect branches and
36 # Test that address-masking sandboxing is added before load instructions.
106 # Test that address-masking sandboxing is added before store instructions.
168 # Test that address-masking sandboxing is added after instructions that change
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| /external/swiftshader/third_party/LLVM/test/Transforms/ScalarRepl/ |
| D | DifferingTypes.ll | 2 ; generated code should perform the appropriate masking operations required
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| /external/llvm/test/Analysis/ValueTracking/ |
| D | known-power-of-two.ll | 10 ; The next 3 lines prevent another fold from masking the bug.
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| /external/mesa3d/src/mesa/main/ |
| D | accum.c | 349 const GLboolean masking = (!ctx->Color.ColorMask[buffer][RCOMP] || in accum_return() local
355 if (masking) in accum_return()
385 if (masking) { in accum_return()
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | mul_int24.ll | 9 ; Make sure we are not masking the inputs
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| D | mad_int24.ll | 9 ; Make sure we aren't masking the inputs.
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| /external/llvm/test/CodeGen/X86/ |
| D | 2011-12-15-vec_shift.ll | 13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-06.ll | 84 ; Check the next value up, which without masking must use a separate
117 ; Check the next value down, which without masking must use a separate
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| D | shift-05.ll | 84 ; Check the next value up, which without masking must use a separate
117 ; Check the next value down, which without masking must use a separate
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| D | shift-07.ll | 84 ; Check the next value up, which without masking must use a separate
117 ; Check the next value down, which without masking must use a separate
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| D | shift-08.ll | 107 ; Check the next value up, which without masking must use a separate
149 ; Check the next value down, which without masking must use a separate
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| D | shift-04.ll | 106 ; Check the next value up, which without masking must use a separate
148 ; Check the next value down, which without masking must use a separate
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| D | addr-01.ll | 79 ; Like f6, but without the masking. This OR doesn't count as a displacement.
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| D | addr-02.ll | 86 ; Like f6, but without the masking. This OR doesn't count as a displacement.
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| /external/clang/lib/CodeGen/ |
| D | README.txt | 14 Bitfields accesses can be shifted to simplify masking and sign
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| /external/icu/icu4c/source/data/translit/ |
| D | Hebr_Latn.txt | 30 # move longer items here to avoid masking
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| D | he_he_Latn_BGN.txt | 53 # Rules moved to front to avoid masking
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| D | dv_dv_Latn_BGN.txt | 150 # SHAVIYANI (placed last to avoid masking)
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| D | Arab_Latn.txt | 62 # longer items moved here to prevent masking
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| D | uz_Cyrl_uz_BGN.txt | 60 # Rules moved to front to avoid masking
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| D | fa_fa_Latn_BGN.txt | 78 # Rules moved to front to avoid masking
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| D | ar_ar_Latn_BGN.txt | 81 # Rules moved to front to avoid masking
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| D | ps_ps_Latn_BGN.txt | 78 # Rules moved to front to avoid masking
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-bitfield-extract.ll | 345 ; and some low bits and a masking operation has to be kept
353 ; Do the masking
373 ; and some low bits and a masking operation has to be kept
382 ; Do the masking
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| /external/libvpx/libvpx/ |
| D | CHANGELOG | 400 Improved activity masking (lower PSNR impact for same SSIM boost)
428 --tune=ssim option to enable activity masking
461 also includes support for "activity masking," which greatly improves
473 Add simple version of activity masking.
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