Searched refs:mflo (Results 1 – 25 of 112) sorted by relevance
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| /external/llvm/test/MC/Mips/ |
| D | macro-ddivu.s | 10 # CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
16 # CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
22 # CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
28 # CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
34 # CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
40 # CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
46 # CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
52 # CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
60 # CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
65 # CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
[all …]
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| D | macro-divu.s | 10 # CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
16 # CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
22 # CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
34 # CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
40 # CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
46 # CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
54 # CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
59 # CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
64 # CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
75 # CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
[all …]
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| D | macro-ddiv.s | 17 # CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
30 # CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
46 # CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
62 # CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
81 # CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
91 # CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
104 # CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
117 # CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
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| D | macro-div.s | 16 # CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
28 # CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
49 # CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
67 # CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
76 # CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
94 # CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
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| D | micromips-16-bit-instructions.s | 44 # CHECK-EL: mflo $9 # encoding: [0x49,0x46]
99 # CHECK-EB: mflo $9 # encoding: [0x46,0x49]
152 mflo $9
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| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | mul.ll | 37 ; M2: mflo $[[T0:[0-9]+]]
50 ; M4: mflo $[[T0:[0-9]+]]
75 ; M2: mflo $[[T0:[0-9]+]]
90 ; M4: mflo $[[T0:[0-9]+]]
116 ; M2: mflo $[[T0:[0-9]+]]
131 ; M4: mflo $[[T0:[0-9]+]]
157 ; M2: mflo $2
176 ; M2: mflo $[[T0:[0-9]+]]
178 ; M2: mflo $[[T1:[0-9]+]]
180 ; M2: mflo $3
[all …]
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| D | udiv.ll | 42 ; NOT-R6: mflo $2
49 ; MMR3: mflo $2
64 ; NOT-R6: mflo $2
71 ; MMR3: mflo $2
86 ; NOT-R6: mflo $2
93 ; MMR3: mflo $2
108 ; NOT-R6: mflo $2
115 ; MMR3: mflo $2
132 ; GP64-NOT-R6: mflo $2
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| D | sdiv.ll | 42 ; NOT-R6: mflo $[[T0:[0-9]+]]
55 ; MMR3: mflo $[[T0:[0-9]+]]
74 ; NOT-R2-R6: mflo $[[T0:[0-9]+]]
81 ; R2-R5: mflo $[[T0:[0-9]+]]
92 ; MMR3: mflo $[[T0:[0-9]+]]
109 ; NOT-R2-R6: mflo $[[T0:[0-9]+]]
116 ; R2-R5: mflo $[[T0:[0-9]+]]
127 ; MMR3: mflo $[[T0:[0-9]+]]
144 ; NOT-R6: mflo $2
151 ; MMR3: mflo $2
[all …]
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| /external/llvm/test/CodeGen/Mips/ |
| D | divrem.ll | 48 ; ACC32: mflo $2
49 ; ACC64: mflo $2
102 ; ACC32: mflo $2
103 ; ACC64: mflo $2
144 ; ACC32: mflo $2
151 ; ACC64: mflo $2
185 ; ACC32: mflo $2
192 ; ACC64: mflo $2
244 ; ACC64: mflo $2
290 ; ACC64: mflo $2
[all …]
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| D | mulll.ll | 16 ; 16: mflo ${{[0-9]+}}
18 ; 16: mflo ${{[0-9]+}}
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| D | mulull.ll | 17 ; 16: mflo ${{[0-9]+}}
19 ; 16: mflo ${{[0-9]+}}
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| D | mips64muldiv.ll | 15 ; ACC: mflo $2
45 ; ACC: mflo $2
55 ; ACC: mflo $2
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| D | madd-msub.ll | 24 ; DSP-DAG: mflo $3, $[[AC]]
70 ; DSP-DAG: mflo $3, $[[AC]]
108 ; DSP-DAG: mflo $3, $[[AC]]
149 ; DSP-DAG: mflo $3, $[[AC]]
195 ; DSP-DAG: mflo $3, $[[AC]]
235 ; DSP-DAG: mflo $3, $[[AC]]
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| D | inlineasm-cnstrnt-reg.ll | 34 ; after the inline expression for a mflo to pull the value out of lo.
39 ; CHECK-NEXT: mflo ${{[0-9]+}}
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| D | divu.ll | 13 ; 16: mflo ${{[0-9]+}}
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| D | mul.ll | 13 ; 16: mflo ${{[0-9]+}}
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| D | div.ll | 13 ; 16: mflo ${{[0-9]+}}
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| D | divu_remu.ll | 17 ; 16: mflo ${{[0-9]+}}
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| D | div_rem.ll | 16 ; 16: mflo ${{[0-9]+}}
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| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| D | sdiv.ll | 26 ; MIPS32: mflo
43 ; MIPS32: mflo
57 ; MIPS32: mflo
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| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | div1.ll | 26 ; CHECK-DAG: mflo $[[RESULT:[0-9]+]]
48 ; CHECK-DAG: mflo $[[RESULT:[0-9]+]]
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| /external/llvm/test/MC/Mips/dsp/ |
| D | valid.s | 58 …mflo $15, $ac0 # CHECK: mflo $15, $ac0 # encoding: [0x00,0x…
60 …mflo $15 # CHECK: mflo $15 # encoding: [0x00,0x…
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| /external/llvm/test/MC/Disassembler/Mips/dsp/ |
| D | valid-el.txt | 4 0x12 0xa8 0x60 0x00 # CHECK: mflo $21, $ac3
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| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | mips64instrs.ll | 90 ; CHECK: mflo
98 ; CHECK: mflo
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| D | 2008-08-01-AsmInline.ll | 3 ; RUN: grep mflo %t | count 1
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