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Searched refs:mtfsb0 (Results 1 – 10 of 10) sorted by relevance

/external/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s392 # CHECK-BE: mtfsb0 31 # encoding: [0xff,0xe0,0x00,0x8c]
393 # CHECK-LE: mtfsb0 31 # encoding: [0x8c,0x00,0xe0,0xff]
394 mtfsb0 31
395 # FIXME: mtfsb0. 31
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-fp.txt342 # CHECK: mtfsb0 31
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCSchedule.td261 // mtfsb0 IntMTFSB0
DPPCInstrInfo.td1125 "mtfsb0 $FM", IntMTFSB0,
/external/v8/src/compiler/ppc/
Dcode-generator-ppc.cc1750 __ mtfsb0(VXCVI); // clear FPSCR:VXCVI bit in AssembleArchInstruction() local
1782 __ mtfsb0(VXCVI); // clear FPSCR:VXCVI bit in AssembleArchInstruction() local
/external/v8/src/ppc/
Dassembler-ppc.h1088 void mtfsb0(FPSCRBit bit, RCBit rc = LeaveRC);
Dconstants-ppc.h1507 V(mtfsb0, MTFSB0, 0xFC00008C) \
Dassembler-ppc.cc2301 void Assembler::mtfsb0(FPSCRBit bit, RCBit rc) { in mtfsb0() function in v8::internal::Assembler
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td2419 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
/external/valgrind/
DNEWS1345 n-i-bz ppc32/64: fix a regression with the mtfsb0/mtfsb1 instructions