| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| D | thumb2-mvn2.ll | 5 ; CHECK: mvns r0, r0
12 ; CHECK: mvns r0, r0
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-mvn2.ll | 5 ; CHECK: mvns r0, r0
12 ; CHECK: mvns r0, r0
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | arm_instructions.s | 54 @ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
55 mvns r1,r2
|
| D | basic-thumb-instructions.s | 384 mvns r6, r3
386 @ CHECK: mvns r6, r3 @ encoding: [0xde,0x43]
|
| D | basic-arm-instructions.s | 991 mvns r3, #7
998 @ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3]
1007 mvns r2, r3
1017 @ CHECK: mvns r2, r3 @ encoding: [0x03,0x20,0xf0,0xe1]
1031 mvns r5, r6, lsr r7
1036 @ CHECK: mvns r5, r6, lsr r7 @ encoding: [0x36,0x57,0xf0,0xe1]
|
| D | basic-thumb2-instructions.s | 1226 mvns r8, #21
1228 mvns r0, #0x3fc0000
1234 @ CHECK: mvns r8, #21 @ encoding: [0x7f,0xf0,0x15,0x08]
1236 @ CHECK: mvns r0, #66846720 @ encoding: [0x7f,0xf0,0x7f,0x70]
1247 mvns r2, r3
1257 @ CHECK: mvns r2, r3 @ encoding: [0xda,0x43]
|
| /external/llvm/test/MC/ARM/ |
| D | arm_instructions.s | 61 @ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
62 mvns r1,r2
|
| D | basic-thumb-instructions.s | 435 mvns r6, r3
437 @ CHECK: mvns r6, r3 @ encoding: [0xde,0x43]
|
| D | basic-thumb2-instructions.s | 1617 mvns r8, #21
1619 mvns r0, #0x3fc0000
1625 @ CHECK: mvns r8, #21 @ encoding: [0x7f,0xf0,0x15,0x08]
1627 @ CHECK: mvns r0, #66846720 @ encoding: [0x7f,0xf0,0x7f,0x70]
1638 mvns r2, r3
1648 @ CHECK: mvns r2, r3 @ encoding: [0xda,0x43]
|
| D | basic-arm-instructions.s | 1533 mvns r3, #7
1551 @ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3]
1560 mvns r2, r3
1570 @ CHECK: mvns r2, r3 @ encoding: [0x03,0x20,0xf0,0xe1]
1584 mvns r5, r6, lsr r7
1589 @ CHECK: mvns r5, r6, lsr r7 @ encoding: [0x36,0x57,0xf0,0xe1]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | minsize-imms.ll | 17 ; CHECK-V6M: mvns r0, [[TMP]] @ encoding: [0xc0,0x43]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 306 # CHECK: mvns r6, r3
|
| D | basic-arm-instructions.txt | 935 # CHECK: mvns r3, #7
936 # CHECK: mvns r11, #240, #30
937 # CHECK: mvns r11, #-2147483638
957 # CHECK: mvns r2, r3
981 # CHECK: mvns r5, r6, lsr r7
|
| D | thumb2.txt | 1168 # CHECK: mvns r8, #21
1170 # CHECK: mvns r0, #66846720
1189 # CHECK: mvns r2, r3
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 289 # CHECK: mvns r6, r3
|
| D | basic-arm-instructions.txt | 828 # CHECK: mvns r3, #7
844 # CHECK: mvns r2, r3
868 # CHECK: mvns r5, r6, lsr r7
|
| D | thumb2.txt | 1051 # CHECK: mvns r8, #21
1053 # CHECK: mvns r0, #66846720
1072 # CHECK: mvns r2, r3
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-operand-rn-t32.cc | 57 M(mvns) \
|
| D | test-assembler-cond-rd-operand-const-a32-cannot-use-pc.cc | 55 M(mvns)
|
| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 57 M(mvns) \
|
| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 57 M(mvns) \
|
| D | test-assembler-cond-rd-operand-const-t32.cc | 57 M(mvns) \
|
| /external/valgrind/none/tests/arm/ |
| D | v6intARM.stdout.exp | 18 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x80000000 N
19 mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 0, cpsr 0x80000000 N
20 mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 0, cpsr 0x00000000
21 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 1, cpsr 0xa0000000 N C
22 mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 1, cpsr 0xa0000000 N C
23 mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 1, cpsr 0x20000000 C
|
| D | v6intThumb.stdout.exp | 115 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
116 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
117 mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
118 mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000
119 mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 0, cpsr 0x00000000
120 mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
121 mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
122 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
123 mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
124 mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x10000000 V
[all …]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2624 void mvns(Condition cond,
2628 void mvns(Register rd, const Operand& operand) { in mvns() function
2629 mvns(al, Best, rd, operand); in mvns()
2631 void mvns(Condition cond, Register rd, const Operand& operand) { in mvns() function
2632 mvns(cond, Best, rd, operand); in mvns()
2634 void mvns(EncodingSize size, Register rd, const Operand& operand) { in mvns() function
2635 mvns(al, size, rd, operand); in mvns()
|