Searched refs:noOfEntries (Results 1 – 7 of 7) sorted by relevance
176 const UINT_32 *pSetting, UINT_32 noOfEntries);179 const UINT_32 *pSetting, UINT_32 noOfEntries);
428 valid = InitTileSettingTable(pRegValue->pTileConfig, pRegValue->noOfEntries); in HwlInitGlobalParams()1308 UINT_32 noOfEntries ///< [in] Numbe of entries in the table above in InitTileSettingTable() argument1313 ADDR_ASSERT(noOfEntries <= TileTableSize); in InitTileSettingTable()1317 if (noOfEntries != 0) in InitTileSettingTable()1319 m_noOfEntries = noOfEntries; in InitTileSettingTable()
1890 valid = InitTileSettingTable(pRegValue->pTileConfig, pRegValue->noOfEntries); in HwlInitGlobalParams()2566 UINT_32 noOfEntries ///< [in] Numbe of entries in the table above in InitTileSettingTable() argument2571 ADDR_ASSERT(noOfEntries <= TileTableSize); in InitTileSettingTable()2575 if (noOfEntries != 0) in InitTileSettingTable()2577 m_noOfEntries = noOfEntries; in InitTileSettingTable()
256 const UINT_32 *pSetting, UINT_32 noOfEntries);
132 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode); in radv_amdgpu_addr_create()
116 regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode); in amdgpu_addr_create()
293 UINT_32 noOfEntries; ///< Number of entries in pTileConfig member