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1 /**************************************************************************
2  *
3  * Copyright 2011 Advanced Micro Devices, Inc.
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 
28 /*
29  * Authors:
30  *      Christian König <christian.koenig@amd.com>
31  *
32  */
33 
34 #ifndef RADEON_UVD_H
35 #define RADEON_UVD_H
36 
37 #include "radeon/radeon_winsys.h"
38 #include "vl/vl_video_buffer.h"
39 
40 /* UVD uses PM4 packet type 0 and 2 */
41 #define RUVD_PKT_TYPE_S(x)		(((unsigned)(x) & 0x3) << 30)
42 #define RUVD_PKT_TYPE_G(x)		(((x) >> 30) & 0x3)
43 #define RUVD_PKT_TYPE_C			0x3FFFFFFF
44 #define RUVD_PKT_COUNT_S(x)		(((unsigned)(x) & 0x3FFF) << 16)
45 #define RUVD_PKT_COUNT_G(x)		(((x) >> 16) & 0x3FFF)
46 #define RUVD_PKT_COUNT_C		0xC000FFFF
47 #define RUVD_PKT0_BASE_INDEX_S(x)	(((unsigned)(x) & 0xFFFF) << 0)
48 #define RUVD_PKT0_BASE_INDEX_G(x)	(((x) >> 0) & 0xFFFF)
49 #define RUVD_PKT0_BASE_INDEX_C		0xFFFF0000
50 #define RUVD_PKT0(index, count)		(RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count))
51 #define RUVD_PKT2()			(RUVD_PKT_TYPE_S(2))
52 
53 /* registers involved with UVD */
54 #define RUVD_GPCOM_VCPU_CMD		0xEF0C
55 #define RUVD_GPCOM_VCPU_DATA0		0xEF10
56 #define RUVD_GPCOM_VCPU_DATA1		0xEF14
57 #define RUVD_ENGINE_CNTL		0xEF18
58 
59 /* UVD commands to VCPU */
60 #define RUVD_CMD_MSG_BUFFER		0x00000000
61 #define RUVD_CMD_DPB_BUFFER		0x00000001
62 #define RUVD_CMD_DECODING_TARGET_BUFFER	0x00000002
63 #define RUVD_CMD_FEEDBACK_BUFFER	0x00000003
64 #define RUVD_CMD_SESSION_CONTEXT_BUFFER	0x00000005
65 #define RUVD_CMD_BITSTREAM_BUFFER	0x00000100
66 #define RUVD_CMD_ITSCALING_TABLE_BUFFER	0x00000204
67 #define RUVD_CMD_CONTEXT_BUFFER		0x00000206
68 
69 /* UVD message types */
70 #define RUVD_MSG_CREATE		0
71 #define RUVD_MSG_DECODE		1
72 #define RUVD_MSG_DESTROY	2
73 
74 /* UVD stream types */
75 #define RUVD_CODEC_H264		0x00000000
76 #define RUVD_CODEC_VC1		0x00000001
77 #define RUVD_CODEC_MPEG2	0x00000003
78 #define RUVD_CODEC_MPEG4	0x00000004
79 #define RUVD_CODEC_H264_PERF	0x00000007
80 #define RUVD_CODEC_H265		0x00000010
81 
82 /* UVD decode target buffer tiling mode */
83 #define RUVD_TILE_LINEAR	0x00000000
84 #define RUVD_TILE_8X4		0x00000001
85 #define RUVD_TILE_8X8		0x00000002
86 #define RUVD_TILE_32AS8		0x00000003
87 
88 /* UVD decode target buffer array mode */
89 #define RUVD_ARRAY_MODE_LINEAR				0x00000000
90 #define RUVD_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED	0x00000001
91 #define RUVD_ARRAY_MODE_1D_THIN				0x00000002
92 #define RUVD_ARRAY_MODE_2D_THIN				0x00000004
93 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR	0x00000004
94 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_TILED		0x00000005
95 
96 /* UVD tile config */
97 #define RUVD_BANK_WIDTH(x)		((x) << 0)
98 #define RUVD_BANK_HEIGHT(x)		((x) << 3)
99 #define RUVD_MACRO_TILE_ASPECT_RATIO(x)	((x) << 6)
100 #define RUVD_NUM_BANKS(x)		((x) << 9)
101 
102 /* H.264 profile definitions */
103 #define RUVD_H264_PROFILE_BASELINE	0x00000000
104 #define RUVD_H264_PROFILE_MAIN		0x00000001
105 #define RUVD_H264_PROFILE_HIGH		0x00000002
106 #define RUVD_H264_PROFILE_STEREO_HIGH	0x00000003
107 #define RUVD_H264_PROFILE_MVC		0x00000004
108 
109 /* VC-1 profile definitions */
110 #define RUVD_VC1_PROFILE_SIMPLE		0x00000000
111 #define RUVD_VC1_PROFILE_MAIN		0x00000001
112 #define RUVD_VC1_PROFILE_ADVANCED	0x00000002
113 
114 struct ruvd_mvc_element {
115 	uint16_t	viewOrderIndex;
116 	uint16_t	viewId;
117 	uint16_t	numOfAnchorRefsInL0;
118 	uint16_t	viewIdOfAnchorRefsInL0[15];
119 	uint16_t	numOfAnchorRefsInL1;
120 	uint16_t	viewIdOfAnchorRefsInL1[15];
121 	uint16_t	numOfNonAnchorRefsInL0;
122 	uint16_t	viewIdOfNonAnchorRefsInL0[15];
123 	uint16_t	numOfNonAnchorRefsInL1;
124 	uint16_t	viewIdOfNonAnchorRefsInL1[15];
125 };
126 
127 struct ruvd_h264 {
128 	uint32_t	profile;
129 	uint32_t	level;
130 
131 	uint32_t	sps_info_flags;
132 	uint32_t	pps_info_flags;
133 	uint8_t		chroma_format;
134 	uint8_t		bit_depth_luma_minus8;
135 	uint8_t		bit_depth_chroma_minus8;
136 	uint8_t		log2_max_frame_num_minus4;
137 
138 	uint8_t		pic_order_cnt_type;
139 	uint8_t		log2_max_pic_order_cnt_lsb_minus4;
140 	uint8_t		num_ref_frames;
141 	uint8_t		reserved_8bit;
142 
143 	int8_t		pic_init_qp_minus26;
144 	int8_t		pic_init_qs_minus26;
145 	int8_t		chroma_qp_index_offset;
146 	int8_t		second_chroma_qp_index_offset;
147 
148 	uint8_t		num_slice_groups_minus1;
149 	uint8_t		slice_group_map_type;
150 	uint8_t		num_ref_idx_l0_active_minus1;
151 	uint8_t		num_ref_idx_l1_active_minus1;
152 
153 	uint16_t	slice_group_change_rate_minus1;
154 	uint16_t	reserved_16bit_1;
155 
156 	uint8_t		scaling_list_4x4[6][16];
157 	uint8_t		scaling_list_8x8[2][64];
158 
159 	uint32_t	frame_num;
160 	uint32_t	frame_num_list[16];
161 	int32_t		curr_field_order_cnt_list[2];
162 	int32_t		field_order_cnt_list[16][2];
163 
164 	uint32_t	decoded_pic_idx;
165 
166 	uint32_t	curr_pic_ref_frame_num;
167 
168 	uint8_t		ref_frame_list[16];
169 
170 	uint32_t	reserved[122];
171 
172 	struct {
173 		uint32_t			numViews;
174 		uint32_t			viewId0;
175 		struct ruvd_mvc_element	mvcElements[1];
176 	} mvc;
177 };
178 
179 struct ruvd_h265 {
180 	uint32_t	sps_info_flags;
181 	uint32_t	pps_info_flags;
182 
183 	uint8_t		chroma_format;
184 	uint8_t		bit_depth_luma_minus8;
185 	uint8_t		bit_depth_chroma_minus8;
186 	uint8_t		log2_max_pic_order_cnt_lsb_minus4;
187 
188 	uint8_t		sps_max_dec_pic_buffering_minus1;
189 	uint8_t		log2_min_luma_coding_block_size_minus3;
190 	uint8_t		log2_diff_max_min_luma_coding_block_size;
191 	uint8_t		log2_min_transform_block_size_minus2;
192 
193 	uint8_t		log2_diff_max_min_transform_block_size;
194 	uint8_t		max_transform_hierarchy_depth_inter;
195 	uint8_t		max_transform_hierarchy_depth_intra;
196 	uint8_t		pcm_sample_bit_depth_luma_minus1;
197 
198 	uint8_t		pcm_sample_bit_depth_chroma_minus1;
199 	uint8_t		log2_min_pcm_luma_coding_block_size_minus3;
200 	uint8_t		log2_diff_max_min_pcm_luma_coding_block_size;
201 	uint8_t		num_extra_slice_header_bits;
202 
203 	uint8_t		num_short_term_ref_pic_sets;
204 	uint8_t		num_long_term_ref_pic_sps;
205 	uint8_t		num_ref_idx_l0_default_active_minus1;
206 	uint8_t		num_ref_idx_l1_default_active_minus1;
207 
208 	int8_t		pps_cb_qp_offset;
209 	int8_t		pps_cr_qp_offset;
210 	int8_t		pps_beta_offset_div2;
211 	int8_t		pps_tc_offset_div2;
212 
213 	uint8_t		diff_cu_qp_delta_depth;
214 	uint8_t		num_tile_columns_minus1;
215 	uint8_t		num_tile_rows_minus1;
216 	uint8_t		log2_parallel_merge_level_minus2;
217 
218 	uint16_t	column_width_minus1[19];
219 	uint16_t	row_height_minus1[21];
220 
221 	int8_t		init_qp_minus26;
222 	uint8_t		num_delta_pocs_ref_rps_idx;
223 	uint8_t		curr_idx;
224 	uint8_t		reserved1;
225 	int32_t		curr_poc;
226 	uint8_t		ref_pic_list[16];
227 	int32_t		poc_list[16];
228 	uint8_t		ref_pic_set_st_curr_before[8];
229 	uint8_t		ref_pic_set_st_curr_after[8];
230 	uint8_t		ref_pic_set_lt_curr[8];
231 
232 	uint8_t		ucScalingListDCCoefSizeID2[6];
233 	uint8_t		ucScalingListDCCoefSizeID3[2];
234 
235 	uint8_t		highestTid;
236 	uint8_t		isNonRef;
237 
238 	uint8_t 	p010_mode;
239 	uint8_t 	msb_mode;
240 	uint8_t 	luma_10to8;
241 	uint8_t 	chroma_10to8;
242 	uint8_t 	sclr_luma10to8;
243 	uint8_t 	sclr_chroma10to8;
244 
245 	uint8_t 	direct_reflist[2][15];
246 };
247 
248 struct ruvd_vc1 {
249 	uint32_t	profile;
250 	uint32_t	level;
251 	uint32_t	sps_info_flags;
252 	uint32_t	pps_info_flags;
253 	uint32_t	pic_structure;
254 	uint32_t	chroma_format;
255 };
256 
257 struct ruvd_mpeg2 {
258 	uint32_t	decoded_pic_idx;
259 	uint32_t	ref_pic_idx[2];
260 
261 	uint8_t		load_intra_quantiser_matrix;
262 	uint8_t		load_nonintra_quantiser_matrix;
263 	uint8_t		reserved_quantiser_alignement[2];
264 	uint8_t		intra_quantiser_matrix[64];
265 	uint8_t		nonintra_quantiser_matrix[64];
266 
267 	uint8_t		profile_and_level_indication;
268 	uint8_t		chroma_format;
269 
270 	uint8_t		picture_coding_type;
271 
272 	uint8_t		reserved_1;
273 
274 	uint8_t		f_code[2][2];
275 	uint8_t		intra_dc_precision;
276 	uint8_t		pic_structure;
277 	uint8_t		top_field_first;
278 	uint8_t		frame_pred_frame_dct;
279 	uint8_t		concealment_motion_vectors;
280 	uint8_t		q_scale_type;
281 	uint8_t		intra_vlc_format;
282 	uint8_t		alternate_scan;
283 };
284 
285 struct ruvd_mpeg4
286 {
287 	uint32_t	decoded_pic_idx;
288 	uint32_t	ref_pic_idx[2];
289 
290 	uint32_t	variant_type;
291 	uint8_t		profile_and_level_indication;
292 
293 	uint8_t		video_object_layer_verid;
294 	uint8_t		video_object_layer_shape;
295 
296 	uint8_t		reserved_1;
297 
298 	uint16_t	video_object_layer_width;
299 	uint16_t	video_object_layer_height;
300 
301 	uint16_t	vop_time_increment_resolution;
302 
303 	uint16_t	reserved_2;
304 
305 	uint32_t	flags;
306 
307 	uint8_t		quant_type;
308 
309 	uint8_t		reserved_3[3];
310 
311 	uint8_t		intra_quant_mat[64];
312 	uint8_t		nonintra_quant_mat[64];
313 
314 	struct {
315 		uint8_t		sprite_enable;
316 
317 		uint8_t		reserved_4[3];
318 
319 		uint16_t	sprite_width;
320 		uint16_t	sprite_height;
321 		int16_t		sprite_left_coordinate;
322 		int16_t		sprite_top_coordinate;
323 
324 		uint8_t		no_of_sprite_warping_points;
325 		uint8_t		sprite_warping_accuracy;
326 		uint8_t		sprite_brightness_change;
327 		uint8_t		low_latency_sprite_enable;
328 	} sprite_config;
329 
330 	struct {
331 		uint32_t	flags;
332 		uint8_t		vol_mode;
333 		uint8_t		reserved_5[3];
334 	} divx_311_config;
335 };
336 
337 /* message between driver and hardware */
338 struct ruvd_msg {
339 
340 	uint32_t	size;
341 	uint32_t	msg_type;
342 	uint32_t	stream_handle;
343 	uint32_t	status_report_feedback_number;
344 
345 	union {
346 		struct {
347 			uint32_t	stream_type;
348 			uint32_t	session_flags;
349 			uint32_t	asic_id;
350 			uint32_t	width_in_samples;
351 			uint32_t	height_in_samples;
352 			uint32_t	dpb_buffer;
353 			uint32_t	dpb_size;
354 			uint32_t	dpb_model;
355 			uint32_t	version_info;
356 		} create;
357 
358 		struct {
359 			uint32_t	stream_type;
360 			uint32_t	decode_flags;
361 			uint32_t	width_in_samples;
362 			uint32_t	height_in_samples;
363 
364 			uint32_t	dpb_buffer;
365 			uint32_t	dpb_size;
366 			uint32_t	dpb_model;
367 			uint32_t	dpb_reserved;
368 
369 			uint32_t	db_offset_alignment;
370 			uint32_t	db_pitch;
371 			uint32_t	db_tiling_mode;
372 			uint32_t	db_array_mode;
373 			uint32_t	db_field_mode;
374 			uint32_t	db_surf_tile_config;
375 			uint32_t	db_aligned_height;
376 			uint32_t	db_reserved;
377 
378 			uint32_t	use_addr_macro;
379 
380 			uint32_t	bsd_buffer;
381 			uint32_t	bsd_size;
382 
383 			uint32_t	pic_param_buffer;
384 			uint32_t	pic_param_size;
385 			uint32_t	mb_cntl_buffer;
386 			uint32_t	mb_cntl_size;
387 
388 			uint32_t	dt_buffer;
389 			uint32_t	dt_pitch;
390 			uint32_t	dt_tiling_mode;
391 			uint32_t	dt_array_mode;
392 			uint32_t	dt_field_mode;
393 			uint32_t	dt_luma_top_offset;
394 			uint32_t	dt_luma_bottom_offset;
395 			uint32_t	dt_chroma_top_offset;
396 			uint32_t	dt_chroma_bottom_offset;
397 			uint32_t	dt_surf_tile_config;
398 			uint32_t	dt_uv_surf_tile_config;
399 			// re-use dt_wa_chroma_top_offset as dt_ext_info for UV pitch in stoney
400 			uint32_t	dt_wa_chroma_top_offset;
401 			uint32_t	dt_wa_chroma_bottom_offset;
402 
403 			uint32_t	reserved[16];
404 
405 			union {
406 				struct ruvd_h264	h264;
407 				struct ruvd_h265	h265;
408 				struct ruvd_vc1		vc1;
409 				struct ruvd_mpeg2	mpeg2;
410 				struct ruvd_mpeg4	mpeg4;
411 
412 				uint32_t info[768];
413 			} codec;
414 
415 			uint8_t		extension_support;
416 			uint8_t		reserved_8bit_1;
417 			uint8_t		reserved_8bit_2;
418 			uint8_t		reserved_8bit_3;
419 			uint32_t	extension_reserved[64];
420 		} decode;
421 	} body;
422 };
423 
424 /* driver dependent callback */
425 typedef struct pb_buffer* (*ruvd_set_dtb)
426 (struct ruvd_msg* msg, struct vl_video_buffer *vb);
427 
428 /* create an UVD decode */
429 struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
430 					     const struct pipe_video_codec *templat,
431 					     ruvd_set_dtb set_dtb);
432 
433 /* fill decoding target field from the luma and chroma surfaces */
434 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
435 			  struct radeon_surf *chroma);
436 #endif
437