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/external/llvm/test/Bitcode/
DbinaryIntInstructions.3.2.ll25 ; CHECK: %res6 = add nuw i1 %x1, %x1
26 %res6 = add nuw i1 %x1, %x1
31 ; CHECK: %res8 = add nuw nsw i1 %x1, %x1
32 %res8 = add nuw nsw i1 %x1, %x1
39 ; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1
40 %res1 = add nuw nsw <2 x i8> %x1, %x1
42 ; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2
43 %res2 = add nuw nsw <3 x i8> %x2, %x2
45 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3
46 %res3 = add nuw nsw <4 x i8> %x3, %x3
[all …]
Dflags.ll15 %u = add nuw i32 %a, 0 ; <i32> [#uses=0]
17 %us = add nuw nsw i32 %a, 0 ; <i32> [#uses=0]
23 %uu = add nuw i32 %a, 0 ; <i32> [#uses=0]
25 %uuss = add nuw nsw i32 %a, 0 ; <i32> [#uses=0]
/external/llvm/test/Assembler/
Dflags.ll7 ; CHECK: %z = add nuw i64 %x, %y
8 %z = add nuw i64 %x, %y
13 ; CHECK: %z = sub nuw i64 %x, %y
14 %z = sub nuw i64 %x, %y
19 ; CHECK: %z = mul nuw i64 %x, %y
20 %z = mul nuw i64 %x, %y
61 ; CHECK: %z = add nuw nsw i64 %x, %y
62 %z = add nuw nsw i64 %x, %y
67 ; CHECK: %z = sub nuw nsw i64 %x, %y
68 %z = sub nuw nsw i64 %x, %y
[all …]
/external/swiftshader/third_party/LLVM/test/Assembler/
Dflags.ll6 ; CHECK: %z = add nuw i64 %x, %y
7 %z = add nuw i64 %x, %y
12 ; CHECK: %z = sub nuw i64 %x, %y
13 %z = sub nuw i64 %x, %y
18 ; CHECK: %z = mul nuw i64 %x, %y
19 %z = mul nuw i64 %x, %y
60 ; CHECK: %z = add nuw nsw i64 %x, %y
61 %z = add nuw nsw i64 %x, %y
66 ; CHECK: %z = sub nuw nsw i64 %x, %y
67 %z = sub nuw nsw i64 %x, %y
[all …]
/external/llvm/test/Transforms/LoadCombine/
Dload-combine.ll11 %4 = shl nuw i64 %3, 56
15 %8 = shl nuw nsw i64 %7, 48
20 %13 = shl nuw nsw i64 %12, 40
25 %18 = shl nuw nsw i64 %17, 32
30 %23 = shl nuw nsw i64 %22, 24
35 %28 = shl nuw nsw i64 %27, 16
40 %33 = shl nuw nsw i64 %32, 8
58 %5 = shl nuw i32 %4, 16
74 %5 = shl nuw i32 %4, 16
90 %5 = shl nuw i32 %4, 16
[all …]
/external/llvm/test/Transforms/LoopVectorize/AArch64/
Dloop-vectorization-factors.ll8 ; CHECK: add nuw nsw <16 x i8>
24 %add = add nuw nsw i32 %conv, 2
28 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
36 ; CHECK: add nuw nsw <8 x i16>
52 %add = add nuw nsw i32 %conv8, 2
56 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
64 ; CHECK: add nuw nsw <8 x i16>
80 %add = add nuw nsw i32 %conv, 2
84 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
110 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
[all …]
/external/llvm/test/Transforms/Reassociate/
Dwrap-flags.ll17 ; CHECK: %mul = mul nuw i32 %i, 4
21 %mul = shl nuw i32 %i, 2
27 ; CHECK: %mul = mul nuw nsw i32 %i, 4
31 %mul = shl nuw nsw i32 %i, 2
42 %add = add nuw i2 %X1, 1
43 %sub = sub nuw nsw i2 %X2, %add
/external/llvm/test/CodeGen/X86/
Dcodegen-prepare-extload.ll37 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2
39 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
46 %add = add nuw i8 %t, 2
97 ; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
99 ; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
102 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
110 %add = add nuw i8 %t, %b
159 ; STRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
161 ; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[TMP]], [[ZEXTC]]
163 ; NONSTRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
[all …]
Davg.ll33 %5 = add nuw nsw <4 x i32> %3, <i32 1, i32 1, i32 1, i32 1>
34 %6 = add nuw nsw <4 x i32> %5, %4
69 %5 = add nuw nsw <8 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
70 %6 = add nuw nsw <8 x i32> %5, %4
95 …%5 = add nuw nsw <16 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i3…
96 %6 = add nuw nsw <16 x i32> %5, %4
122 …%5 = add nuw nsw <32 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i3…
123 %6 = add nuw nsw <32 x i32> %5, %4
141 …%5 = add nuw nsw <64 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i3…
142 %6 = add nuw nsw <64 x i32> %5, %4
[all …]
/external/llvm/test/Transforms/LoopStrengthReduce/
Dsext-ind-var.ll30 %index32 = add nuw nsw i32 %i, %offset
35 %nexti = add nuw nsw i32 %i, 1
63 %index32 = sub nuw nsw i32 %i, %offset
68 %nexti = add nuw nsw i32 %i, 1
95 %index32 = mul nuw nsw i32 %i, %stride
100 %nexti = add nuw nsw i32 %i, 1
128 %index32 = shl nuw nsw i32 %i, 7
129 %index32mul = mul nuw nsw i32 %index32, 3
134 %nexti = add nuw nsw i32 %i, 1
/external/swiftshader/third_party/LLVM/test/Bitcode/
Dflags.ll14 %u = add nuw i32 %a, 0 ; <i32> [#uses=0]
16 %us = add nuw nsw i32 %a, 0 ; <i32> [#uses=0]
22 %uu = add nuw i32 %a, 0 ; <i32> [#uses=0]
24 %uuss = add nuw nsw i32 %a, 0 ; <i32> [#uses=0]
/external/llvm/test/Analysis/Delinearization/
Dparameter_addrec_product.ll10 ; CHECK: ArrayRef[{0,+,1}<nuw><nsw><%bb2>][{0,+,1}<nuw><nsw><%bb4>]
32 %tmp = add nuw nsw i64 %i.0, %j.0
44 %tmp14 = add nuw nsw i64 %j.0, 1
51 %tmp17 = add nuw nsw i64 %i.0, 1
/external/llvm/test/Analysis/ScalarEvolution/
Dscev-expander-incorrect-nowrap.ll12 ; The only use for idx.mirror is to induce an nuw for %idx. It does
13 ; not induce an nuw for %idx.inc
20 %idx.mirror.inc = add nuw i8 %idx.mirror, 1
24 ; CHECK-NOT: %indvars.iv.next = add nuw nsw i32 %indvars.iv, 1
Dpr22179.ll18 %inc = add nuw i8 %storemerge1, 1
19 ; CHECK: %inc = add nuw i8 %storemerge1, 1
20 ; CHECK-NEXT: --> {1,+,1}<nuw><%loop>
21 ; CHECK-NOT: --> {1,+,1}<nuw><nsw><%loop>
Dflags-from-poison.ll38 ; Example where an add should get the nuw flag.
39 define void @test-add-nuw(float* %input, i32 %offset, i32 %numIterations) {
40 ; CHECK-LABEL: @test-add-nuw
47 ; CHECK: --> {%offset,+,1}<nuw>
48 %index32 = add nuw i32 %i, %offset
51 %nexti = add nuw i32 %i, 1
60 define void @test-add-nuw-from-icmp(float* %input, i32 %offset,
62 ; CHECK-LABEL: @test-add-nuw-from-icmp
69 ; CHECK: --> {%offset,+,1}<nuw>
70 %index32 = add nuw i32 %i, %offset
[all …]
/external/llvm/test/Transforms/InstCombine/
Ddemand_shrink_nsw.ll6 ; CHECK: %v35 = add nuw i32 %v34, 1362915575
8 ; CHECK: add nuw i32 %v42, 1533579450
15 %v35 = add nuw i32 %v34, 3510399223
20 %v41 = shl nsw nuw i32 %v40, 1
/external/llvm/test/CodeGen/Hexagon/
Dcsr-func-usedef.ll44 %add = add nuw nsw i32 %conv, %conv17
45 %add10 = add nuw nsw i32 %add, %conv8
46 %add12 = add nuw nsw i32 %add10, %conv9
47 %add14 = add nuw nsw i32 %add12, %conv11
48 %add16 = add nuw nsw i32 %add14, %conv13
49 %add18 = add nuw nsw i32 %add16, %conv15
63 %add38 = add nuw nsw i32 %conv36, %conv37
/external/llvm/test/Transforms/InstSimplify/
Dimplies.ll87 ; i +_{nuw} C <u L ==> i <u L
92 %iplus1 = add nuw i32 %i, 1
131 ; i +_{nuw} 1 <u L ==> i < L +_{nuw} 1
136 %iplus1 = add nuw i32 %i, 1
137 %len.plus.one = add nuw i32 %length.i, 1
144 ; i +_{nuw} C <u L ==> i < L, even if C is negative
149 %iplus1 = add nuw i32 %i, -100
209 %large = add nuw i32 %x, 100
210 %small = add nuw i32 %x, 90
232 ; CHECK: [[LARGE:%.*]] = add nuw i32 %x, 100
[all …]
Dexact-nsw-nuw.ll9 %D = shl nuw i32 %C, %B
18 %D = shl nuw i32 %C, %B
26 %D = shl nuw i32 %C, %B
33 %C = shl nuw i32 %A, %B
/external/swiftshader/third_party/LLVM/test/Transforms/InstSimplify/
Dexact-nsw-nuw.ll9 %D = shl nuw i32 %C, %B
18 %D = shl nuw i32 %C, %B
26 %D = shl nuw i32 %C, %B
33 %C = shl nuw i32 %A, %B
/external/llvm/test/CodeGen/PowerPC/
Drlwimi-dyn-and.ll12 %shl161 = shl nuw nsw i32 %conv67.reload, 15
15 %shl170 = shl nuw nsw i32 %conv169, 7
33 %shl161 = shl nuw nsw i32 %conv67.reload, 15
36 %shl170 = shl nuw nsw i32 %conv169, 7
/external/llvm/test/Analysis/BasicAA/
Dsequential-gep.ll7 %add = add nsw nuw i32 %addend, %knownnonzero
17 %add = add nsw nuw i32 %addend, %knownnonzero
27 %add = add nsw nuw i32 %addend, %knownnonzero
37 %add = add nsw nuw i32 %addend, %knownnonzero
47 %add = add nsw nuw i32 %addend, %knownnonzero
/external/llvm/test/CodeGen/SystemZ/
Ddag-combine-01.ll22 %indvars.iv.next25 = add nuw nsw i64 %indvars.iv24, 1
47 %4 = add nuw nsw i64 %3, %1
55 %10 = add nuw nsw i64 %9, %2
66 %indvars.iv.next.i = add nuw nsw i64 %indvars.iv.i, 1
72 %indvars.iv.next58.i = add nuw nsw i64 %indvars.iv57.i, 1
73 %indvars.iv.next20 = add nuw nsw i32 %indvars.iv19, 1
78 %inc9 = add nuw nsw i32 %i.116, 1
91 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
/external/llvm/test/DebugInfo/COFF/
Dvirtual-method-kinds.ll120 …nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor7* @"\01??_R0?AUC@@@8" to i64), i64 ptrtoint (i8* @__Im…
124 …t %rtti.ClassHierarchyDescriptor { i32 0, i32 0, i32 3, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (…
125 …nuw nsw (i64 ptrtoint (%rtti.BaseClassDescriptor* @"\01??_R1A@?0A@EA@C@@8" to i64), i64 ptrtoint (…
126 …nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor7* @"\01??_R0?AUC@@@8" to i64), i64 ptrtoint (i8* @__Im…
127 …nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor7* @"\01??_R0?AUB@@@8" to i64), i64 ptrtoint (i8* @__Im…
129 …t %rtti.ClassHierarchyDescriptor { i32 0, i32 0, i32 2, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (…
130 …nuw nsw (i64 ptrtoint (%rtti.BaseClassDescriptor* @"\01??_R1A@?0A@EA@B@@8" to i64), i64 ptrtoint (…
131 …nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor7* @"\01??_R0?AUA@@@8" to i64), i64 ptrtoint (i8* @__Im…
133 …t %rtti.ClassHierarchyDescriptor { i32 0, i32 0, i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (…
134 @"\01??_R2A@@8" = linkonce_odr constant [2 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.…
[all …]
/external/llvm/test/Transforms/LoopStrengthReduce/AArch64/
Dlsr-memset.ll49 %2 = shl nuw nsw i64 %1, 8
51 %3 = shl nuw nsw i64 %1, 16
53 %4 = shl nuw nsw i64 %1, 24
54 %5 = shl nuw nsw i64 %1, 32
56 %6 = shl nuw nsw i64 %1, 40
58 %7 = shl nuw nsw i64 %1, 48
59 %8 = shl nuw i64 %1, 56

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