Searched refs:opN (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/test/Bitcode/ |
| D | mdnodes-distinct-nodes-first.ll | 6 ; bitcode. !1 is referenced as opN=1.
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| D | mdnodes-distinct-in-post-order.ll | 6 ; bitcode. !3 is referenced as opN=3.
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| D | mdnodes-distinct-nodes-break-cycles.ll | 14 ; bitcode. !3 is referenced as opN=3.
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| D | mdnodes-in-post-order.ll | 9 ; bitcode. !3 is referenced as opN=3.
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| /external/python/cpython2/Doc/reference/ |
| D | expressions.rst | 1092 *opN* are comparison operators, then ``a op1 b op2 c ... y opN z`` is equivalent
1093 to ``a op1 b and b op2 c and ... y opN z``, except that each expression is
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| /external/valgrind/VEX/priv/ |
| D | guest_arm64_toIR.c | 10337 IROp opN = Iop_INVALID; in dis_AdvSIMD_scalar_two_reg_misc() local
10341 opN = mkVecQNARROWUNSS(size); nm = "sqxtn"; zWiden = False; in dis_AdvSIMD_scalar_two_reg_misc()
10344 opN = mkVecQNARROWUNUU(size); nm = "uqxtn"; in dis_AdvSIMD_scalar_two_reg_misc()
10347 opN = mkVecQNARROWUNSU(size); nm = "sqxtun"; in dis_AdvSIMD_scalar_two_reg_misc()
10353 size, unop(Iop_64UtoV128, unop(opN, mkexpr(src)))); in dis_AdvSIMD_scalar_two_reg_misc()
12490 IROp opN = mkVecNARROWUN(size); in dis_AdvSIMD_two_reg_misc() local
12492 assign(resN, unop(Iop_64UtoV128, unop(opN, getQReg128(nn)))); in dis_AdvSIMD_two_reg_misc()
12510 IROp opN = Iop_INVALID; in dis_AdvSIMD_two_reg_misc() local
12514 opN = mkVecQNARROWUNSS(size); nm = "sqxtn"; zWiden = False; in dis_AdvSIMD_two_reg_misc()
12517 opN = mkVecQNARROWUNUU(size); nm = "uqxtn"; in dis_AdvSIMD_two_reg_misc()
[all …]
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| D | guest_mips_toIR.c | 1153 static void calculateFCSR(UInt fs, UInt ft, UInt inst, Bool sz32, UInt opN) in calculateFCSR() argument
1175 if (opN == 1) { /* Unary operation. */ in calculateFCSR()
1198 } else if (opN == 2) { /* Binary operation. */ in calculateFCSR()
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