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Searched refs:pTileInfo (Results 1 – 11 of 11) sorted by relevance

/external/mesa3d/src/amd/addrlib/r800/
Degbaddrlib.cpp96 ADDR_TILEINFO* pTileInfo = &tileInfoDef; in DispatchComputeSurfaceInfo() local
117 ADDR_ASSERT(pOut->pTileInfo); in DispatchComputeSurfaceInfo()
119 if (pOut->pTileInfo != NULL) in DispatchComputeSurfaceInfo()
121 pTileInfo = pOut->pTileInfo; in DispatchComputeSurfaceInfo()
125 if (pIn->pTileInfo != NULL) in DispatchComputeSurfaceInfo()
127 if (pTileInfo != pIn->pTileInfo) in DispatchComputeSurfaceInfo()
129 *pTileInfo = *pIn->pTileInfo; in DispatchComputeSurfaceInfo()
134 memset(pTileInfo, 0, sizeof(ADDR_TILEINFO)); in DispatchComputeSurfaceInfo()
144 pIn->pTileInfo, in DispatchComputeSurfaceInfo()
145 pTileInfo, in DispatchComputeSurfaceInfo()
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Degbaddrlib.h108 UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo,
123 BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const;
182 ADDR_TILEINFO* pTileInfo) const = 0;
191 UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const = 0;
198 ADDR_TILEINFO* pTileInfo) const = 0;
237 ADDR_TILEINFO* pTileInfo) const;
246 ADDR_TILEINFO* pTileInfo) const;
250 UINT_32 base256b, ADDR_TILEINFO* pTileInfo,
255 UINT_64 baseAddr, ADDR_TILEINFO* pTileInfo) const;
259 ADDR_TILEINFO* pTileInfo) const;
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Dsiaddrlib.cpp105 const ADDR_TILEINFO* pTileInfo ///< [in] Tile info in HwlGetPipes()
110 if (pTileInfo) in HwlGetPipes()
112 numPipes = GetPipePerSurf(pTileInfo->pipeConfig); in HwlGetPipes()
186 ADDR_TILEINFO* pTileInfo ///< [in] Tile info in ComputePipeFromCoord()
208 switch (pTileInfo->pipeConfig) in ComputePipeFromCoord()
731 ADDR_TILEINFO* pTileInfo ///< [in] tile info in HwlComputeTileDataWidthAndHeightLinear()
734 ADDR_ASSERT(pTileInfo != NULL); in HwlComputeTileDataWidthAndHeightLinear()
742 if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32) || in HwlComputeTileDataWidthAndHeightLinear()
743 (pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) || in HwlComputeTileDataWidthAndHeightLinear()
744 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x32_16x16)) in HwlComputeTileDataWidthAndHeightLinear()
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Dciaddrlib.cpp298 UINT_32 numOfPipes = HwlGetPipes(pIn->pTileInfo); in HwlComputeCmaskAddrFromCoord()
299 UINT_32 numOfBanks = pIn->pTileInfo->banks; in HwlComputeCmaskAddrFromCoord()
657 if (pOut->pTileInfo == NULL) in HwlComputeFmaskInfo()
659 pOut->pTileInfo = &tileInfo; in HwlComputeFmaskInfo()
696 macroModeIndex = HwlComputeMacroModeIndex(tileIndex, flags, bpp, numSamples, pOut->pTileInfo); in HwlComputeFmaskInfo()
699 fmaskIn.pTileInfo = pOut->pTileInfo; in HwlComputeFmaskInfo()
708 HwlPostCheckTileIndex(pOut->pTileInfo, pIn->tileMode, ADDR_NON_DISPLAYABLE, in HwlComputeFmaskInfo()
713 if (pOut->pTileInfo == &tileInfo) in HwlComputeFmaskInfo()
715 pOut->pTileInfo = NULL; in HwlComputeFmaskInfo()
969 ADDR_TILEINFO* pTileInfo = pTileInfoOut; in HwlSetupTileInfo() local
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Dsiaddrlib.h102 ADDR_TILEINFO* pTileInfo, UINT_32* pBitPosition) const;
107 ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
128 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
137 ADDR_TILEINFO* pTileInfo) const;
139 virtual UINT_32 HwlGetPipes(const ADDR_TILEINFO* pTileInfo) const;
182 ADDR_TILEINFO* pTileInfo) const in HwlSanityCheckMacroTiled() argument
199 ADDR_TILEINFO* pTileInfo) const;
202 UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const;
225 ADDR_TILEINFO* pTileInfo) const in HwlReduceBankWidthHeight() argument
Dciaddrlib.h113 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
117 ADDR_TILEINFO* pTileInfo, AddrTileMode* pTileMode = NULL, AddrTileType* pTileType = NULL
162 UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
/external/mesa3d/src/amd/addrlib/core/
Daddrlib.cpp425 if (pIn->pTileInfo) in ComputeSurfaceInfo()
427 tileInfoNull = *pIn->pTileInfo; in ComputeSurfaceInfo()
429 localIn.pTileInfo = &tileInfoNull; in ComputeSurfaceInfo()
515 ADDR_ASSERT(localIn.pTileInfo); in ComputeSurfaceInfo()
528 localIn.pTileInfo, in ComputeSurfaceInfo()
537 localIn.pTileInfo, in ComputeSurfaceInfo()
685 input.pTileInfo = &tileInfoNull; in ComputeSurfaceAddrFromCoord()
695 input.pTileInfo, in ComputeSurfaceAddrFromCoord()
703 input.pTileInfo, &input.tileMode, &input.tileType); in ComputeSurfaceAddrFromCoord()
765 input.pTileInfo = &tileInfoNull; in ComputeSurfaceCoordFromAddr()
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Daddrlib.h346 UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo,
356 BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const = 0;
429 ADDR_TILEINFO* pTileInfo,
438 ADDR_TILEINFO* pTileInfo, UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pCmaskBytes,
444 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
450 BOOL_32 isHeight8, ADDR_TILEINFO* pTileInfo,
456 ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
479 UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
485 UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel, in HwlPadDimensions() argument
526 const ADDR_TILEINFO* pTileInfo) const;
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/external/mesa3d/src/amd/addrlib/
Daddrinterface.h502 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate member
549 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input member
619 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data member
713 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data member
800 ADDR_TILEINFO* pTileInfo; ///< Tile info member
868 ADDR_TILEINFO* pTileInfo; ///< Tile info member
929 ADDR_TILEINFO* pTileInfo; ///< Tile info member
1010 ADDR_TILEINFO* pTileInfo; ///< Tile info member
1081 ADDR_TILEINFO* pTileInfo; ///< Tile info member
1140 ADDR_TILEINFO* pTileInfo; ///< Tile info member
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/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c226 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo; in compute_level()
255 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo; in compute_level()
329 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut; in amdgpu_surface_init()
451 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn; in amdgpu_surface_init()
509 surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1; in amdgpu_surface_init()
514 surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth; in amdgpu_surface_init()
515 surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight; in amdgpu_surface_init()
516 surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio; in amdgpu_surface_init()
517 surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes; in amdgpu_surface_init()
518 surf->num_banks = AddrSurfInfoOut.pTileInfo->banks; in amdgpu_surface_init()
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/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.c246 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo; in radv_compute_level()
313 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut; in radv_amdgpu_winsys_surface_init()
417 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn; in radv_amdgpu_winsys_surface_init()
468 surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1; in radv_amdgpu_winsys_surface_init()
473 surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth; in radv_amdgpu_winsys_surface_init()
474 surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight; in radv_amdgpu_winsys_surface_init()
475 surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio; in radv_amdgpu_winsys_surface_init()
476 surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes; in radv_amdgpu_winsys_surface_init()
477 surf->num_banks = AddrSurfInfoOut.pTileInfo->banks; in radv_amdgpu_winsys_surface_init()
507 AddrSurfInfoOut.pTileInfo->tileSplitBytes; in radv_amdgpu_winsys_surface_init()