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Searched refs:pmull (Results 1 – 25 of 48) sorted by relevance

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/external/boringssl/ios-aarch64/crypto/fipsmodule/
Dghashv8-armx64.S31 pmull v0.1q,v20.1d,v20.1d
34 pmull v1.1q,v16.1d,v16.1d
40 pmull v18.1q,v0.1d,v19.1d //1st phase
47 pmull v0.1q,v0.1d,v19.1d
72 pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
75 pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
81 pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
88 pmull v0.1q,v0.1d,v19.1d
140 pmull v4.1q,v20.1d,v7.1d //H·Ii+1
149 pmull v0.1q,v22.1d,v3.1d //H^2.lo·Xi.lo
[all …]
/external/boringssl/linux-aarch64/crypto/fipsmodule/
Dghashv8-armx64.S32 pmull v0.1q,v20.1d,v20.1d
35 pmull v1.1q,v16.1d,v16.1d
41 pmull v18.1q,v0.1d,v19.1d //1st phase
48 pmull v0.1q,v0.1d,v19.1d
73 pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
76 pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
82 pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
89 pmull v0.1q,v0.1d,v19.1d
141 pmull v4.1q,v20.1d,v7.1d //H·Ii+1
150 pmull v0.1q,v22.1d,v3.1d //H^2.lo·Xi.lo
[all …]
/external/boringssl/linux-arm/crypto/fipsmodule/
Dghashv8-armx32.S32 .byte 0xa8,0x0e,0xa8,0xf2 @ pmull q0,q12,q12
35 .byte 0xa0,0x2e,0xa0,0xf2 @ pmull q1,q8,q8
41 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase
48 .byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
73 .byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo
76 .byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
82 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
89 .byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
142 .byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ H·Ii+1
151 .byte 0x86,0x0e,0xac,0xf2 @ pmull q0,q14,q3 @ H^2.lo·Xi.lo
[all …]
/external/boringssl/ios-arm/crypto/fipsmodule/
Dghashv8-armx32.S33 .byte 0xa8,0x0e,0xa8,0xf2 @ pmull q0,q12,q12
36 .byte 0xa0,0x2e,0xa0,0xf2 @ pmull q1,q8,q8
42 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase
49 .byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
76 .byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo
79 .byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
85 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
92 .byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
147 .byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ H·Ii+1
156 .byte 0x86,0x0e,0xac,0xf2 @ pmull q0,q14,q3 @ H^2.lo·Xi.lo
[all …]
/external/llvm/test/MC/AArch64/
Darm64-verbose-vector-case.s3 pmull v8.8h, v8.8b, v8.8b label
5 pmull v8.1q, v8.1d, v8.1d label
12 pmull v8.8H, v8.8B, v8.8B label
14 pmull v8.1Q, v8.1D, v8.1D label
Darm64-diagno-predicate.s15 pmull v0.1q, v1.1d, v2.1d
Dneon-3vdiff.s285 pmull v0.8h, v1.8b, v2.8b
286 pmull v0.1q, v1.1d, v2.1d
Darm64-advsimd.s1931 pmull.8h v0, v0, v0
1933 pmull.1q v2, v3, v4
1935 pmull v2.1q, v3.1d, v4.1d
1938 ; CHECK: pmull.8h v0, v0, v0 ; encoding: [0x00,0xe0,0x20,0x0e]
1940 ; CHECK: pmull.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x0e]
1942 ; CHECK: pmull.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x0e]
2084 ; pmull verbose mode aliases
2085 pmull v8.8h, v8.8b, v8.8b
2087 pmull v8.1q, v8.1d, v8.1d
2089 ; CHECK: pmull.8h v8, v8, v8 ; encoding: [0x08,0xe1,0x28,0x0e]
[all …]
Dneon-diagnostics.s2594 pmull v0.8h, v1.8h, v2.8b
2600 pmull v0.1q, v1.2d, v2.2d
2607 pmull v0.4s, v1.4h, v2.4h
2608 pmull v0.2d, v1.2s, v2.2s
/external/libyuv/files/unit_test/testdata/
Djuno.txt8 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
/external/llvm/test/CodeGen/X86/
Davx512dqvl-intrinsics.ll9 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…
20 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %pas…
30 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…
40 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…
52 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %pas…
63 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…
75 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…
89 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %pas…
102 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…
105 declare <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
[all …]
Dstack-folding-mmx.ll428 %2 = call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %a, x86_mmx %b) nounwind readnone
431 declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone
Davx512bwvl-intrinsics.ll2393 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …
2404 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …
2414 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …
2424 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …
2436 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …
2447 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …
2451 declare <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
2458 …%res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zero…
2469 …%res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %pas…
2479 …%res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zero…
[all …]
Dmmx-intrinsics.ll600 declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone
610 %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
625 %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
Davx512-intrinsics.ll2584 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …
2595 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …
2605 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …
2615 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …
2627 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …
2638 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …
2650 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …
2664 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …
2677 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …
2681 declare <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dmmx-arith.ll257 …%tmp52 = tail call x86_mmx @llvm.x86.mmx.pmull.w( x86_mmx %tmp45, x86_mmx %tmp51 ) ; <x86_mmx> [#…
305 declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx)
Dmmx-builtins.ll555 declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone
564 %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
578 %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
/external/swiftshader/third_party/subzero/src/
DIceAssemblerX86Base.h368 void pmull(Type Ty, XmmRegister dst, XmmRegister src);
369 void pmull(Type Ty, XmmRegister dst, const Address &src);
DIceAssemblerX86BaseImpl.h877 void AssemblerX86Base<TraitsType>::pmull(Type Ty, XmmRegister dst, in pmull() function
894 void AssemblerX86Base<TraitsType>::pmull(Type Ty, XmmRegister dst, in pmull() function
/external/swiftshader/third_party/subzero/tests_lit/assembler/x86/
Dopcode_register_encodings.ll2 ; those for pmull vary more wildly depending on operand size (rather than
/external/llvm/test/CodeGen/AArch64/
Darm64-vmul.ll112 ;CHECK: pmull.8h
115 %tmp3 = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
119 declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
1829 …%res = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhsvec) no…
1841 …%res = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhs.high) …
2015 ; CHECK: pmull.1q
Darm64-neon-3vdiff.ll3 declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>)
1791 ; CHECK: pmull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1793 %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %a, <8 x i8> %b)
1803 …%vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %shuffle.i.i, <8 x i8> %s…
1809 ; CHECK: pmull {{v[0-9]+}}.1q, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d
/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DXmmArith.cpp284 pmull, *, int, Size); \ in TEST_F()
289 pmull, *, int, Size); \ in TEST_F()
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DXmmArith.cpp281 pmull, *, int, Size); \ in TEST_F()
286 pmull, *, int, Size); \ in TEST_F()
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2204 # CHECK: pmull.8h v0, v0, v0
2206 # CHECK: pmull.1q v0, v0, v0

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