| /external/llvm/test/CodeGen/ARM/ |
| D | sat-arith.ll | 14 ; CHECK-LABEL: qsub
15 define i32 @qsub() nounwind {
18 ; CHECK-ARM: qsub [[R0]], [[R1]], [[R0]]
20 %tmp = call i32 @llvm.arm.qsub(i32 128, i32 8)
61 declare i32 @llvm.arm.qsub(i32, i32) nounwind
|
| /external/arm-neon-tests/ |
| D | ref_dsp.c | 105 sres = qsub(svar1, svar2); in exec_dsp()
111 sres = qsub(svar1, svar2); in exec_dsp()
117 sres = qsub(svar1, svar2); in exec_dsp()
123 sres = qsub(svar1, svar2); in exec_dsp()
129 sres = qsub(svar1, svar2); in exec_dsp()
135 sres = qsub(svar1, svar2); in exec_dsp()
141 sres = qsub(svar1, svar2); in exec_dsp()
147 sres = qsub(svar1, svar2); in exec_dsp()
|
| D | ref-rvct-all.txt | 7980 qsub(0x1, 0x2) = 0xffffffff sat 0
7981 qsub(0xffffffff, 0xfffffffe) = 0x1 sat 0
7982 qsub(0xffffffff, 0x2) = 0xfffffffd sat 0
7983 qsub(0x7000, 0xffff9000) = 0xe000 sat 0
7984 qsub(0x8fff, 0xffff7001) = 0x11ffe sat 0
7985 qsub(0x70000000, 0x90000000) = 0x7fffffff sat 1
7986 qsub(0x8fffffff, 0x70000001) = 0x80000000 sat 1
7987 qsub(0, 0x80000000) = 0x7fffffff sat 1
|
| /external/valgrind/none/tests/arm/ |
| D | v6media.stdout.exp | 3867 qsub r0, r1, r2 :: rd 0x80000001 rm 0x00000000, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[…
3868 qsub r0, r1, r2 :: rd 0x80000002 rm 0x00000001, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[…
3869 qsub r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[…
3870 qsub r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[…
3871 qsub r0, r1, r2 :: rd 0xfff1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[…
3872 qsub r0, r1, r2 :: rd 0x000e0004 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[…
3873 qsub r0, r1, r2 :: rd 0x0004000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[…
3874 qsub r0, r1, r2 :: rd 0xfffbfff1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[…
3875 qsub r0, r1, r2 :: rd 0x0ddd2e96 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[…
3876 qsub r0, r1, r2 :: rd 0xbc54a9aa rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[…
[all …]
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-t32.cc | 108 M(qsub)
|
| D | test-assembler-cond-rd-rn-rm-a32.cc | 109 M(qsub)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 32 def qsub : SubRegIndex<64>;
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1222 qsub r1, r2, r3
1229 @ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
|
| D | basic-thumb2-instructions.s | 1475 qsub r1, r2, r3
1483 @ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1]
|
| /external/valgrind/VEX/priv/ |
| D | guest_arm64_toIR.c | 8085 IRTemp src, mask, maskn, nsub, qsub; in math_SQABS() local
8086 src = mask = maskn = nsub = qsub = IRTemp_INVALID; in math_SQABS()
8087 newTempsV128_7(&src, &mask, &maskn, &nsub, &qsub, nabs, qabs); in math_SQABS()
8092 assign(qsub, binop(mkVecQSUBS(size), mkV128(0x0000), mkexpr(src))); in math_SQABS()
8097 binop(Iop_AndV128, mkexpr(qsub), mkexpr(mask)), in math_SQABS()
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2763 void qsub(Condition cond, Register rd, Register rm, Register rn);
2764 void qsub(Register rd, Register rm, Register rn) { qsub(al, rd, rm, rn); } in qsub() function
|
| D | disasm-aarch32.h | 873 void qsub(Condition cond, Register rd, Register rm, Register rn);
|
| D | assembler-aarch32.cc | 7987 void Assembler::qsub(Condition cond, Register rd, Register rm, Register rn) { in qsub() function in vixl::aarch32::Assembler
8004 Delegate(kQsub, &Assembler::qsub, cond, rd, rm, rn); in qsub()
|
| D | disasm-aarch32.cc | 2206 void Disassembler::qsub(Condition cond, Register rd, Register rm, Register rn) { in qsub() function in vixl::aarch32::Disassembler
21139 qsub(CurrentCond(), in DecodeT32()
57642 qsub(condition, in DecodeA32()
|
| D | macro-assembler-aarch32.h | 3093 qsub(cond, rd, rm, rn); in Qsub()
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1902 qsub r1, r2, r3
1910 @ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1]
|
| D | basic-arm-instructions.s | 1829 qsub r1, r2, r3
1836 @ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1058 # CHECK: qsub r1, r2, r3
|
| D | thumb2.txt | 1275 # CHECK: qsub r1, r2, r3
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1414 # CHECK: qsub r1, r2, r3
|
| D | basic-arm-instructions.txt | 1175 # CHECK: qsub r1, r2, r3
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1941 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
|
| D | ARMInstrInfo.td | 3163 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2146 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
|
| D | ARMInstrInfo.td | 3564 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
|