| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 31 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
45 ldrb r11,[r1,#1]
50 orr r9,r9,r11,lsl#16
70 ldrb r11,[r1,#1]
75 orr r9,r9,r11,lsl#16
95 ldrb r11,[r1,#1]
100 orr r9,r9,r11,lsl#16
120 ldrb r11,[r1,#1]
125 orr r9,r9,r11,lsl#16
145 ldrb r11,[r1,#1]
[all …]
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 32 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
46 ldrb r11,[r1,#1]
51 orr r9,r9,r11,lsl#16
71 ldrb r11,[r1,#1]
76 orr r9,r9,r11,lsl#16
96 ldrb r11,[r1,#1]
101 orr r9,r9,r11,lsl#16
121 ldrb r11,[r1,#1]
126 orr r9,r9,r11,lsl#16
146 ldrb r11,[r1,#1]
[all …]
|
| /external/boringssl/src/util/fipstools/testdata/x86_64-GOTRewrite/ |
| D | out.s | 7 # WAS leaq OPENSSL_ia32cap_P(%rip), %r11
10 leaq OPENSSL_ia32cap_addr_delta(%rip), %r11
11 addq (%r11), %r11
42 # WAS movq stderr@GOTPCREL(%rip), %r11
45 leaq stderr_GOTPCREL_external(%rip), %r11
46 addq (%r11), %r11
47 movq (%r11), %r11
50 # WAS movq foo@GOTPCREL(%rip), %r11
51 leaq .Lfoo_local_target(%rip), %r11
72 # WAS cmoveq stderr@GOTPCREL(%rip), %r11
[all …]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | frame-09.ll | 1 ; Test the handling of the frame pointer (%r11).
5 ; We should always initialise %r11 when FP elimination is disabled.
10 ; CHECK: stmg %r11, %r15, 88(%r15)
11 ; CHECK: .cfi_offset %r11, -72
14 ; CHECK: lgr %r11, %r15
15 ; CHECK: .cfi_def_cfa_register %r11
16 ; CHECK: lmg %r11, %r15, 88(%r11)
23 ; to %r11 rather than %r15.
26 ; CHECK: stmg %r11, %r15, 88(%r15)
27 ; CHECK: .cfi_offset %r11, -72
[all …]
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-rd-rn-rm-a32.cc | 101 {{r2, r11, r11}, false, al, "r2 r11 r11", "r2_r11_r11"},
104 {{r3, r14, r11}, false, al, "r3 r14 r11", "r3_r14_r11"},
119 {{r11, r12, r2}, false, al, "r11 r12 r2", "r11_r12_r2"},
123 {{r11, r8, r9}, false, al, "r11 r8 r9", "r11_r8_r9"},
124 {{r6, r3, r11}, false, al, "r6 r3 r11", "r6_r3_r11"},
132 {{r8, r11, r0}, false, al, "r8 r11 r0", "r8_r11_r0"},
137 {{r3, r11, r7}, false, al, "r3 r11 r7", "r3_r11_r7"},
140 {{r13, r11, r11}, false, al, "r13 r11 r11", "r13_r11_r11"},
158 {{r5, r6, r11}, false, al, "r5 r6 r11", "r5_r6_r11"},
169 {{r14, r11, r0}, false, al, "r14 r11 r0", "r14_r11_r0"},
[all …]
|
| D | test-assembler-rd-rn-rm-t32.cc | 101 {{r2, r11, r11}, false, al, "r2 r11 r11", "r2_r11_r11"},
104 {{r3, r14, r11}, false, al, "r3 r14 r11", "r3_r14_r11"},
119 {{r11, r12, r2}, false, al, "r11 r12 r2", "r11_r12_r2"},
123 {{r11, r8, r9}, false, al, "r11 r8 r9", "r11_r8_r9"},
124 {{r6, r3, r11}, false, al, "r6 r3 r11", "r6_r3_r11"},
132 {{r8, r11, r0}, false, al, "r8 r11 r0", "r8_r11_r0"},
137 {{r3, r11, r7}, false, al, "r3 r11 r7", "r3_r11_r7"},
140 {{r13, r11, r11}, false, al, "r13 r11 r11", "r13_r11_r11"},
158 {{r5, r6, r11}, false, al, "r5 r6 r11", "r5_r6_r11"},
169 {{r14, r11, r0}, false, al, "r14 r11 r0", "r14_r11_r0"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc | 96 {{mi, r11, r11, r4}, true, mi, "mi r11 r11 r4", "mi_r11_r11_r4"},
100 {{vc, r11, r11, r0}, true, vc, "vc r11 r11 r0", "vc_r11_r11_r0"},
101 {{le, r6, r6, r11}, true, le, "le r6 r6 r11", "le_r6_r6_r11"},
104 {{hi, r11, r11, r1}, true, hi, "hi r11 r11 r1", "hi_r11_r11_r1"},
105 {{cc, r0, r0, r11}, true, cc, "cc r0 r0 r11", "cc_r0_r0_r11"},
108 {{gt, r14, r14, r11}, true, gt, "gt r14 r14 r11", "gt_r14_r14_r11"},
114 {{ls, r14, r14, r11}, true, ls, "ls r14 r14 r11", "ls_r14_r14_r11"},
118 {{le, r11, r11, r4}, true, le, "le r11 r11 r4", "le_r11_r11_r4"},
131 {{lt, r2, r2, r11}, true, lt, "lt r2 r2 r11", "lt_r2_r2_r11"},
134 {{vs, r13, r13, r11}, true, vs, "vs r13 r13 r11", "vs_r13_r13_r11"},
[all …]
|
| D | test-macro-assembler-cond-rd-rn-t32.cc | 96 {{lt, r11, r10}, "lt, r11, r10", "lt_r11_r10"},
101 {{vc, r7, r11}, "vc, r7, r11", "vc_r7_r11"},
105 {{le, r1, r11}, "le, r1, r11", "le_r1_r11"},
108 {{cs, r2, r11}, "cs, r2, r11", "cs_r2_r11"},
124 {{cs, r11, r3}, "cs, r11, r3", "cs_r11_r3"},
128 {{al, r14, r11}, "al, r14, r11", "al_r14_r11"},
138 {{vs, r11, r2}, "vs, r11, r2", "vs_r11_r2"},
139 {{ls, r11, r0}, "ls, r11, r0", "ls_r11_r0"},
144 {{vs, r4, r11}, "vs, r4, r11", "vs_r4_r11"},
150 {{hi, r11, r11}, "hi, r11, r11", "hi_r11_r11"},
[all …]
|
| D | test-macro-assembler-cond-rd-rn-a32.cc | 96 {{lt, r11, r10}, "lt, r11, r10", "lt_r11_r10"},
101 {{vc, r7, r11}, "vc, r7, r11", "vc_r7_r11"},
105 {{le, r1, r11}, "le, r1, r11", "le_r1_r11"},
108 {{cs, r2, r11}, "cs, r2, r11", "cs_r2_r11"},
124 {{cs, r11, r3}, "cs, r11, r3", "cs_r11_r3"},
128 {{al, r14, r11}, "al, r14, r11", "al_r14_r11"},
138 {{vs, r11, r2}, "vs, r11, r2", "vs_r11_r2"},
139 {{ls, r11, r0}, "ls, r11, r0", "ls_r11_r0"},
144 {{vs, r4, r11}, "vs, r4, r11", "vs_r4_r11"},
150 {{hi, r11, r11}, "hi, r11, r11", "hi_r11_r11"},
[all …]
|
| D | test-assembler-cond-rd-rn-rm-a32.cc | 158 {{le, r11, r6, r2}, false, al, "le r11 r6 r2", "le_r11_r6_r2"},
172 {{ge, r4, r13, r11}, false, al, "ge r4 r13 r11", "ge_r4_r13_r11"},
182 {{cs, r14, r11, r13}, false, al, "cs r14 r11 r13", "cs_r14_r11_r13"},
192 {{hi, r11, r5, r9}, false, al, "hi r11 r5 r9", "hi_r11_r5_r9"},
195 {{al, r5, r4, r11}, false, al, "al r5 r4 r11", "al_r5_r4_r11"},
196 {{pl, r11, r11, r2}, false, al, "pl r11 r11 r2", "pl_r11_r11_r2"},
201 {{cs, r3, r11, r10}, false, al, "cs r3 r11 r10", "cs_r3_r11_r10"},
202 {{ls, r11, r4, r0}, false, al, "ls r11 r4 r0", "ls_r11_r4_r0"},
203 {{hi, r11, r8, r9}, false, al, "hi r11 r8 r9", "hi_r11_r8_r9"},
209 {{vc, r8, r11, r6}, false, al, "vc r8 r11 r6", "vc_r8_r11_r6"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-t32.cc | 129 {{{al, r12, r9, r11}, false, al, "al r12 r9 r11", "al_r12_r9_r11"},
133 {{al, r11, r2, r4}, false, al, "al r11 r2 r4", "al_r11_r2_r4"},
135 {{al, r11, r6, r9}, false, al, "al r11 r6 r9", "al_r11_r6_r9"},
136 {{al, r8, r7, r11}, false, al, "al r8 r7 r11", "al_r8_r7_r11"},
144 {{al, r14, r7, r11}, false, al, "al r14 r7 r11", "al_r14_r7_r11"},
145 {{al, r11, r4, r14}, false, al, "al r11 r4 r14", "al_r11_r4_r14"},
150 {{al, r0, r11, r14}, false, al, "al r0 r11 r14", "al_r0_r11_r14"},
157 {{al, r8, r14, r11}, false, al, "al r8 r14 r11", "al_r8_r14_r11"},
159 {{al, r14, r11, r6}, false, al, "al r14 r11 r6", "al_r14_r11_r6"},
160 {{al, r9, r2, r11}, false, al, "al r9 r2 r11", "al_r9_r2_r11"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-t32-in-it-block.cc | 107 {{eq, r0, r11}, true, eq, "eq r0 r11", "eq_r0_r11"},
122 {{eq, r1, r11}, true, eq, "eq r1 r11", "eq_r1_r11"},
137 {{eq, r2, r11}, true, eq, "eq r2 r11", "eq_r2_r11"},
152 {{eq, r3, r11}, true, eq, "eq r3 r11", "eq_r3_r11"},
167 {{eq, r4, r11}, true, eq, "eq r4 r11", "eq_r4_r11"},
182 {{eq, r5, r11}, true, eq, "eq r5 r11", "eq_r5_r11"},
197 {{eq, r6, r11}, true, eq, "eq r6 r11", "eq_r6_r11"},
212 {{eq, r7, r11}, true, eq, "eq r7 r11", "eq_r7_r11"},
227 {{eq, r8, r11}, true, eq, "eq r8 r11", "eq_r8_r11"},
242 {{eq, r9, r11}, true, eq, "eq r9 r11", "eq_r9_r11"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc | 117 {{al, r11, r13, r14, ROR, 8},
122 {{al, r3, r12, r11, ROR, 16},
127 {{al, r0, r11, r6, ROR, 24},
137 {{al, r14, r4, r11, ROR, 16},
162 {{al, r1, r11, r10, ROR, 0},
232 {{al, r3, r7, r11, ROR, 0},
252 {{al, r0, r11, r11, ROR, 16},
287 {{al, r4, r7, r11, ROR, 16},
297 {{al, r1, r11, r2, ROR, 0},
312 {{al, r5, r11, r12, ROR, 0},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-rs-t32.cc | 98 {{al, r11, r2, ASR, r10},
112 {{al, r6, r11, ASR, r8}, false, al, "al r6 r11 ASR r8", "al_r6_r11_ASR_r8"},
128 {{al, r11, r0, ASR, r14},
133 {{al, r12, r11, ROR, r7},
143 {{al, r11, r7, ROR, r0}, false, al, "al r11 r7 ROR r0", "al_r11_r7_ROR_r0"},
149 {{al, r9, r12, LSR, r11},
156 {{al, r10, r6, ROR, r11},
169 {{al, r6, r11, LSR, r1}, false, al, "al r6 r11 LSR r1", "al_r6_r11_LSR_r1"},
208 {{al, r10, r11, ASR, r7},
219 {{al, r11, r13, LSR, r3},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc | 126 {{vs, r11, r0, r14, ROR, r1},
131 {{vc, r5, r0, r11, ROR, r4},
201 {{mi, r11, r14, r7, LSR, r5},
231 {{vs, r14, r14, r11, LSR, r6},
336 {{vc, r11, r9, r14, LSR, r12},
351 {{cs, r9, r9, r7, LSL, r11},
361 {{ne, r7, r11, r1, ROR, r2},
421 {{al, r2, r14, r11, ROR, r0},
426 {{eq, r11, r1, r6, ASR, r10},
431 {{vs, r11, r9, r5, LSL, r10},
[all …]
|
| /external/tremolo/Tremolo/ |
| D | mdctARM.s | 188 STMFD r13!,{r4,r6-r11,r14}
198 LDR r11,[r9],#4 @ r11= *wL++
203 SMULL r14,r11,r12,r11 @ (r14,r11) = *l * *wL++
205 ADD r6, r6, r11
216 LDMFD r13!,{r4,r6-r11,PC}
227 STMFD r13!,{r4,r6-r11,r14}
237 LDR r11,[r9],#4 @ r11= *wL++
242 SMULL r14,r11,r12,r11 @ (r14,r11) = *l * *wL++
244 SUB r6, r6, r11
255 LDMFD r13!,{r4,r6-r11,PC}
[all …]
|
| D | mdctLARM.s | 186 STMFD r13!,{r4,r6-r11,r14}
198 LDRB r11,[r9],#1 @ r11= *wL++
202 MUL r11,r12,r11 @ r11 = *l * *wL++
204 MLA r6, r7, r6, r11 @ r6 = *--r * *--wR
215 LDMFD r13!,{r4,r6-r11,PC}
226 STMFD r13!,{r4,r6-r11,r14}
237 LDRB r11,[r9],#1 @ r11= *wL++
242 MUL r11,r12,r11 @ (r14,r11) = *l * *wL++
245 SUB r6, r6, r11
256 LDMFD r13!,{r4,r6-r11,PC}
[all …]
|
| D | bitwiseARM.s | 45 STMFD r13!,{r10,r11,r14}
56 LDRLT r11,[r3,#4]! @ r11= ptr[1]
60 ORRLT r10,r10,r11,LSL r14 @ r10= Next 32 bits.
64 LDMFD r13!,{r10,r11,PC}
80 MOV r11,#1
83 RSB r11,r11,r11,LSL r5 @ r11= mask
84 AND r10,r10,r11 @ r10= first r5 bits
88 LDR r11,[r0,#12] @ r11= head = b->head
92 LDR r11,[r11,#12] @ r11= head = head->next
95 CMP r11,#0
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_intra_pred_chroma_ver.s | 124 lsl r11, r3, #2
126 add r11, r11, #0xfffffff0
134 vst2.8 {d22,d23}, [r2], r11
135 vst2.8 {d22,d23}, [r5], r11
136 vst2.8 {d22,d23}, [r8], r11
137 vst2.8 {d22,d23}, [r10], r11
147 vst2.8 {d22,d23}, [r2], r11
148 vst2.8 {d22,d23}, [r5], r11
149 vst2.8 {d22,d23}, [r8], r11
150 vst2.8 {d22,d23}, [r10], r11
[all …]
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| /external/python/cpython2/Modules/_ctypes/libffi/src/microblaze/ |
| D | sysv.S | 118 rsubi r11, r22, FFI_TYPE_STRUCT
119 beqi r11, ffi_call_SYSV_end
122 rsubi r11, r23, 1
123 beqi r11, ffi_call_SYSV_store8
126 rsubi r11, r23, 2
127 beqi r11, ffi_call_SYSV_store16
130 rsubi r11, r23, 4
131 beqi r11, ffi_call_SYSV_store32
134 rsubi r11, r23, 8
135 beqi r11, ffi_call_SYSV_store64
[all …]
|
| /external/boringssl/mac-x86_64/crypto/fipsmodule/ |
| D | x86_64-mont5.S | 36 movq %rsp,%r11
49 subq %r10,%r11
50 andq $-4096,%r11
51 leaq (%r10,%r11,1),%rsp
52 movq (%rsp),%r11
59 movq (%rsp),%r11
212 movq %rdx,%r11
228 addq %r11,%r13
229 movq %r10,%r11
236 addq %rax,%r11
[all …]
|
| /external/boringssl/linux-x86_64/crypto/fipsmodule/ |
| D | x86_64-mont5.S | 37 movq %rsp,%r11
50 subq %r10,%r11
51 andq $-4096,%r11
52 leaq (%r10,%r11,1),%rsp
53 movq (%rsp),%r11
60 movq (%rsp),%r11
213 movq %rdx,%r11
229 addq %r11,%r13
230 movq %r10,%r11
237 addq %rax,%r11
[all …]
|
| /external/llvm/test/MC/X86/ |
| D | x86_64-bmi-encoding.s | 9 blsmskq %r11, %r10
25 blsiq %r11, %r10
41 blsrq %r11, %r10
57 andnq (%rax), %r11, %r10
73 bextrq %r12, %r11, %r10
89 bzhiq %r12, %r11, %r10
101 pextq %r12, %r11, %r10
105 pextq (%rax), %r11, %r10
117 pdepq %r12, %r11, %r10
121 pdepq (%rax), %r11, %r10
[all …]
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| /external/llvm/test/CodeGen/ARM/ |
| D | ehabi.ll | 158 ; CHECK-FP: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
159 ; CHECK-FP: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
160 ; CHECK-FP: .setfp r11, sp, #28
161 ; CHECK-FP: add r11, sp, #28
170 ; CHECK-FP-ELIM: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
171 ; CHECK-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
180 ; CHECK-V7-FP: .save {r4, r10, r11, lr}
181 ; CHECK-V7-FP: push {r4, r10, r11, lr}
182 ; CHECK-V7-FP: .setfp r11, sp, #8
183 ; CHECK-V7-FP: add r11, sp, #8
[all …]
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| /external/boringssl/src/crypto/fipsmodule/bn/asm/ |
| D | x86_64-mont5.pl | 60 $hi0="%r11";
84 leaq OPENSSL_ia32cap_P(%rip),%r11
85 mov 8(%r11),%r11d
107 mov %rsp,%r11
120 sub %r10,%r11
121 and \$-4096,%r11
122 lea (%r10,%r11),%rsp
123 mov (%rsp),%r11
130 mov (%rsp),%r11
448 my @A=("%r10","%r11");
[all …]
|