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Searched refs:r24 (Results 1 – 25 of 47) sorted by relevance

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/external/linux-kselftest/tools/testing/selftests/powerpc/pmu/ebb/
Dbusy_loop.S22 std r24, 80(%r1)
69 li r24, 0x2424
70 std r24, -248(%r1)
129 cmpwi r24, 0x2424
166 li r24, 0xef
230 ld r24, -248(%r1)
231 cmpwi r24, 0x2424
262 ld r24, 80(%r1)
/external/libunwind/src/ia64/
DGinstall_cursor.S92 ld8 r24 = [r3], 2*LOC_SIZE // r24 = loc[IA64_REG_FR24]
107 and r24 = -4, r24
114 ldf.fill f24 = [r24] // f24 restored (don't touch no more)
192 ld8 r24 = [r2], (LC_LOC_OFF - F5_LOC_OFF) // r24 = f5_loc
199 and r24 = -4, r24
219 ldf.fill f5 = [r24] // f5 restored (don't touch no more)
Ducontext_i.h61 #define rRSC r24
/external/llvm/test/MC/Hexagon/
DasmMap.s26 #CHECK: 416bc818 { if (p1) r24 = memuh(r11{{ *}}+{{ *}}#0)
27 if (p1) r24=memuh(r11)
182 #CHECK: a1d8ca00 { memd(r24{{ *}}+{{ *}}#0) = r11:10
183 memd(r24)=r11:10
239 #CHECK: 4718d803 if (!p3.new) r3 = memb(r24{{ *}}+{{ *}}#0)
241 if (!p3.new) r3=memb(r24)
311 #CHECK: 47d8c80e if (!p1.new) r15:14 = memd(r24{{ *}}+{{ *}}#0)
313 if (!p1.new) r15:14=memd(r24)
317 #CHECK: 3918e045 if (p2.new) memb(r24{{ *}}+{{ *}}#0)=#-27
319 if (p2.new) memb(r24)=#-27
[all …]
Dv60-vmpy1.s14 #CHECK: 1918ced6 { v22.h = vdmpy(v14.ub,{{ *}}r24.b) }
15 v22.h=vdmpy(v14.ub,r24.b)
32 #CHECK: 1918de1c { v29:28.h = vtmpy(v31:30.b,{{ *}}r24.b) }
33 v29:28.h=vtmpy(v31:30.b,r24.b)
Dv60-vmem.s80 #CHECK: 29b8d5c4 { if (p2) vmemu(r24++#-3) = v4 }
82 if (p2) vmemu(r24++#-3)=v4
348 #CHECK: 28f8d17a if(!p2) vmem(r24+#1):nt = v4.new }
351 if(!p2)vmem(r24+#1):nt=v4.new
/external/linux-kselftest/tools/testing/selftests/powerpc/include/
Dgpr_asm.h23 std r24,(top_pos - 56)(%r1); \
43 ld r24,(top_pos - 56)(%r1); \
84 ld r24,80(r3)
/external/llvm/test/CodeGen/Hexagon/
Dpic-regusage.ll16 …2},~{r13},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r2…
38 …2},~{r13},~{r14},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r2…
57 …3},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26}"(i32…
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/MBlaze/
Dmblaze_operands.txt79 # CHECK: add r24, r24, r24
/external/swiftshader/third_party/LLVM/test/MC/MBlaze/
Dmblaze_operands.s133 add r24, r24, r24
/external/linux-kselftest/tools/testing/selftests/powerpc/switch_endian/
Dcheck.S71 addi r9,r15,24 # check r24
72 cmpd r9,r24
Dswitch_endian_test.S50 addi r24, r15, 24
/external/llvm/test/CodeGen/PowerPC/
Dr31.ll6 …2},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r2…
D2016-04-16-ADD8TLS.ll10 …2},={r14},={r15},={r16},={r17},={r18},={r19},={r20},={r21},={r22},={r23},={r24},={r25},={r26},={r2…
41 …},{r11},{r12},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r21},{r22},{r23},{r24},{r25},{r26},{r27},…
/external/compiler-rt/lib/tsan/rtl/
Dtsan_ppc_regs.h25 #define r24 24 macro
Dtsan_rtl_ppc64.S85 std r24,104(r3)
230 std r24,104(r3)
/external/llvm/test/MC/PowerPC/
Dppc64-regs.s30 #CHECK: .cfi_offset r24, 200
147 .cfi_offset r24,200
/external/llvm/test/DebugInfo/SystemZ/
Deh_frame.s62 # DW_CFA_offset: r24 at cfa-224
/external/valgrind/VEX/auxprogs/
Dgenoffsets.c218 GENOFFSET(MIPS32,mips32,r24); in foo()
255 GENOFFSET(MIPS64,mips64,r24); in foo()
/external/syslinux/gnu-efi/gnu-efi-3.0/inc/protocol/ia64/
Deficontext.h92 UINT64 r24; member
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td69 def R24 : AVRReg<24, "r24">, DwarfRegNum<[24]>;
94 def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>;
/external/llvm/test/CodeGen/AArch64/
Dghc-cc.ll10 @r3 = external global i64 ; assigned to register: r24
/external/syslinux/gnu-efi/gnu-efi-3.0/gnuefi/
Dreloc_ia64.S86 #define r_addend r24
/external/llvm/test/CodeGen/Mips/msa/
Dspill.ll99 %r24 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r23, <16 x i8> %24)
100 %r25 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r24, <16 x i8> %25)
248 %r24 = call <8 x i16> @llvm.mips.addv.h(<8 x i16> %r23, <8 x i16> %24)
249 %r25 = call <8 x i16> @llvm.mips.addv.h(<8 x i16> %r24, <8 x i16> %25)
397 %r24 = call <4 x i32> @llvm.mips.addv.w(<4 x i32> %r23, <4 x i32> %24)
398 %r25 = call <4 x i32> @llvm.mips.addv.w(<4 x i32> %r24, <4 x i32> %25)
546 %r24 = call <2 x i64> @llvm.mips.addv.d(<2 x i64> %r23, <2 x i64> %24)
547 %r25 = call <2 x i64> @llvm.mips.addv.d(<2 x i64> %r24, <2 x i64> %25)
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeRegisterInfo.td66 def R24 : MBlazeGPRReg< 24, "r24">, DwarfRegNum<[24]>;

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