| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc | 99 {{ls, r4, r3, r6}, true, ls, "ls r4 r3 r6", "ls_r4_r3_r6"},
106 {{gt, r6, r4, r3}, true, gt, "gt r6 r4 r3", "gt_r6_r4_r3"},
108 {{eq, r4, r6, r0}, true, eq, "eq r4 r6 r0", "eq_r4_r6_r0"},
109 {{mi, r2, r6, r1}, true, mi, "mi r2 r6 r1", "mi_r2_r6_r1"},
111 {{hi, r6, r0, r2}, true, hi, "hi r6 r0 r2", "hi_r6_r0_r2"},
117 {{eq, r6, r0, r6}, true, eq, "eq r6 r0 r6", "eq_r6_r0_r6"},
122 {{cc, r1, r6, r7}, true, cc, "cc r1 r6 r7", "cc_r1_r6_r7"},
125 {{lt, r6, r3, r3}, true, lt, "lt r6 r3 r3", "lt_r6_r3_r3"},
127 {{ge, r6, r2, r3}, true, ge, "ge r6 r2 r3", "ge_r6_r2_r3"},
128 {{cc, r5, r6, r6}, true, cc, "cc r5 r6 r6", "cc_r5_r6_r6"},
[all …]
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| D | test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc | 101 {{eq, r0, r6, r0}, true, eq, "eq r0 r6 r0", "eq_r0_r6_r0"},
109 {{eq, r1, r6, r1}, true, eq, "eq r1 r6 r1", "eq_r1_r6_r1"},
117 {{eq, r2, r6, r2}, true, eq, "eq r2 r6 r2", "eq_r2_r6_r2"},
125 {{eq, r3, r6, r3}, true, eq, "eq r3 r6 r3", "eq_r3_r6_r3"},
133 {{eq, r4, r6, r4}, true, eq, "eq r4 r6 r4", "eq_r4_r6_r4"},
141 {{eq, r5, r6, r5}, true, eq, "eq r5 r6 r5", "eq_r5_r6_r5"},
143 {{eq, r6, r0, r6}, true, eq, "eq r6 r0 r6", "eq_r6_r0_r6"},
144 {{eq, r6, r1, r6}, true, eq, "eq r6 r1 r6", "eq_r6_r1_r6"},
145 {{eq, r6, r2, r6}, true, eq, "eq r6 r2 r6", "eq_r6_r2_r6"},
146 {{eq, r6, r3, r6}, true, eq, "eq r6 r3 r6", "eq_r6_r3_r6"},
[all …]
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| D | test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc | 106 {{ge, r6, r6, r1}, true, ge, "ge r6 r6 r1", "ge_r6_r6_r1"},
112 {{hi, r6, r6, r3}, true, hi, "hi r6 r6 r3", "hi_r6_r6_r3"},
113 {{ge, r7, r7, r6}, true, ge, "ge r7 r7 r6", "ge_r7_r7_r6"},
120 {{pl, r0, r0, r6}, true, pl, "pl r0 r0 r6", "pl_r0_r0_r6"},
122 {{cc, r3, r3, r6}, true, cc, "cc r3 r3 r6", "cc_r3_r3_r6"},
141 {{hi, r0, r0, r6}, true, hi, "hi r0 r0 r6", "hi_r0_r0_r6"},
154 {{vs, r6, r6, r3}, true, vs, "vs r6 r6 r3", "vs_r6_r6_r3"},
166 {{ls, r6, r6, r1}, true, ls, "ls r6 r6 r1", "ls_r6_r6_r1"},
168 {{ls, r6, r6, r7}, true, ls, "ls r6 r6 r7", "ls_r6_r6_r7"},
171 {{pl, r7, r7, r6}, true, pl, "pl r7 r7 r6", "pl_r7_r7_r6"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc | 96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"},
103 {{le, r6, r6, ASR, r6}, true, le, "le r6 r6 ASR r6", "le_r6_r6_ASR_r6"},
104 {{hi, r6, r6, ROR, r5}, true, hi, "hi r6 r6 ROR r5", "hi_r6_r6_ROR_r5"},
105 {{le, r3, r3, ASR, r6}, true, le, "le r3 r3 ASR r6", "le_r3_r3_ASR_r6"},
109 {{le, r5, r5, LSR, r6}, true, le, "le r5 r5 LSR r6", "le_r5_r5_LSR_r6"},
110 {{cs, r0, r0, ASR, r6}, true, cs, "cs r0 r0 ASR r6", "cs_r0_r0_ASR_r6"},
112 {{hi, r5, r5, LSL, r6}, true, hi, "hi r5 r5 LSL r6", "hi_r5_r5_LSL_r6"},
113 {{ls, r6, r6, LSL, r3}, true, ls, "ls r6 r6 LSL r3", "ls_r6_r6_LSL_r3"},
119 {{ls, r6, r6, LSR, r0}, true, ls, "ls r6 r6 LSR r0", "ls_r6_r6_LSR_r0"},
121 {{cc, r1, r1, LSL, r6}, true, cc, "cc r1 r1 LSL r6", "cc_r1_r1_LSL_r6"},
[all …]
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| D | test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc | 1633 {{al, r6, r6, 0}, false, al, "al r6 r6 0", "al_r6_r6_0"},
1634 {{al, r6, r6, 1}, false, al, "al r6 r6 1", "al_r6_r6_1"},
1635 {{al, r6, r6, 2}, false, al, "al r6 r6 2", "al_r6_r6_2"},
1636 {{al, r6, r6, 3}, false, al, "al r6 r6 3", "al_r6_r6_3"},
1637 {{al, r6, r6, 4}, false, al, "al r6 r6 4", "al_r6_r6_4"},
1638 {{al, r6, r6, 5}, false, al, "al r6 r6 5", "al_r6_r6_5"},
1639 {{al, r6, r6, 6}, false, al, "al r6 r6 6", "al_r6_r6_6"},
1640 {{al, r6, r6, 7}, false, al, "al r6 r6 7", "al_r6_r6_7"},
1641 {{al, r6, r6, 8}, false, al, "al r6 r6 8", "al_r6_r6_8"},
1642 {{al, r6, r6, 9}, false, al, "al r6 r6 9", "al_r6_r6_9"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc | 101 {{eq, r0, r6}, true, eq, "eq r0 r6", "eq_r0_r6"},
109 {{eq, r1, r6}, true, eq, "eq r1 r6", "eq_r1_r6"},
117 {{eq, r2, r6}, true, eq, "eq r2 r6", "eq_r2_r6"},
125 {{eq, r3, r6}, true, eq, "eq r3 r6", "eq_r3_r6"},
133 {{eq, r4, r6}, true, eq, "eq r4 r6", "eq_r4_r6"},
141 {{eq, r5, r6}, true, eq, "eq r5 r6", "eq_r5_r6"},
143 {{eq, r6, r0}, true, eq, "eq r6 r0", "eq_r6_r0"},
144 {{eq, r6, r1}, true, eq, "eq r6 r1", "eq_r6_r1"},
145 {{eq, r6, r2}, true, eq, "eq r6 r2", "eq_r6_r2"},
146 {{eq, r6, r3}, true, eq, "eq r6 r3", "eq_r6_r3"},
[all …]
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| D | test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc | 101 {{eq, r0, r6, 0}, true, eq, "eq r0 r6 0", "eq_r0_r6_0"},
109 {{eq, r1, r6, 0}, true, eq, "eq r1 r6 0", "eq_r1_r6_0"},
117 {{eq, r2, r6, 0}, true, eq, "eq r2 r6 0", "eq_r2_r6_0"},
125 {{eq, r3, r6, 0}, true, eq, "eq r3 r6 0", "eq_r3_r6_0"},
133 {{eq, r4, r6, 0}, true, eq, "eq r4 r6 0", "eq_r4_r6_0"},
141 {{eq, r5, r6, 0}, true, eq, "eq r5 r6 0", "eq_r5_r6_0"},
143 {{eq, r6, r0, 0}, true, eq, "eq r6 r0 0", "eq_r6_r0_0"},
144 {{eq, r6, r1, 0}, true, eq, "eq r6 r1 0", "eq_r6_r1_0"},
145 {{eq, r6, r2, 0}, true, eq, "eq r6 r2 0", "eq_r6_r2_0"},
146 {{eq, r6, r3, 0}, true, eq, "eq r6 r3 0", "eq_r6_r3_0"},
[all …]
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| D | test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc | 99 {{ls, r1, r6, 0}, true, ls, "ls r1 r6 0", "ls_r1_r6_0"},
102 {{vs, r5, r6, 7}, true, vs, "vs r5 r6 7", "vs_r5_r6_7"},
106 {{lt, r6, r7, 1}, true, lt, "lt r6 r7 1", "lt_r6_r7_1"},
116 {{ls, r6, r6, 4}, true, ls, "ls r6 r6 4", "ls_r6_r6_4"},
122 {{ls, r6, r3, 0}, true, ls, "ls r6 r3 0", "ls_r6_r3_0"},
125 {{eq, r6, r1, 4}, true, eq, "eq r6 r1 4", "eq_r6_r1_4"},
126 {{gt, r6, r0, 1}, true, gt, "gt r6 r0 1", "gt_r6_r0_1"},
135 {{le, r4, r6, 6}, true, le, "le r4 r6 6", "le_r4_r6_6"},
142 {{ne, r6, r3, 0}, true, ne, "ne r6 r3 0", "ne_r6_r3_0"},
149 {{hi, r2, r6, 0}, true, hi, "hi r2 r6 0", "hi_r2_r6_0"},
[all …]
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| D | test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc | 145 {{al, r0, r6, 0}, false, al, "al r0 r6 0", "al_r0_r6_0"},
146 {{al, r0, r6, 1}, false, al, "al r0 r6 1", "al_r0_r6_1"},
147 {{al, r0, r6, 2}, false, al, "al r0 r6 2", "al_r0_r6_2"},
148 {{al, r0, r6, 3}, false, al, "al r0 r6 3", "al_r0_r6_3"},
149 {{al, r0, r6, 4}, false, al, "al r0 r6 4", "al_r0_r6_4"},
150 {{al, r0, r6, 5}, false, al, "al r0 r6 5", "al_r0_r6_5"},
151 {{al, r0, r6, 6}, false, al, "al r0 r6 6", "al_r0_r6_6"},
152 {{al, r0, r6, 7}, false, al, "al r0 r6 7", "al_r0_r6_7"},
209 {{al, r1, r6, 0}, false, al, "al r1 r6 0", "al_r1_r6_0"},
210 {{al, r1, r6, 1}, false, al, "al r1 r6 1", "al_r1_r6_1"},
[all …]
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| D | test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc | 98 {{vc, r6, r6, 138}, true, vc, "vc r6 r6 138", "vc_r6_r6_138"},
100 {{ge, r6, r6, 181}, true, ge, "ge r6 r6 181", "ge_r6_r6_181"},
108 {{le, r6, r6, 39}, true, le, "le r6 r6 39", "le_r6_r6_39"},
124 {{ge, r6, r6, 88}, true, ge, "ge r6 r6 88", "ge_r6_r6_88"},
137 {{cs, r6, r6, 78}, true, cs, "cs r6 r6 78", "cs_r6_r6_78"},
149 {{eq, r6, r6, 158}, true, eq, "eq r6 r6 158", "eq_r6_r6_158"},
158 {{mi, r6, r6, 99}, true, mi, "mi r6 r6 99", "mi_r6_r6_99"},
161 {{hi, r6, r6, 74}, true, hi, "hi r6 r6 74", "hi_r6_r6_74"},
172 {{lt, r6, r6, 229}, true, lt, "lt r6 r6 229", "lt_r6_r6_229"},
192 {{vs, r6, r6, 79}, true, vs, "vs r6 r6 79", "vs_r6_r6_79"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc | 96 {{{ge, r7, r6, LSR, 20}, true, ge, "ge r7 r6 LSR 20", "ge_r7_r6_LSR_20"},
97 {{gt, r4, r6, LSR, 32}, true, gt, "gt r4 r6 LSR 32", "gt_r4_r6_LSR_32"},
98 {{hi, r6, r7, LSR, 29}, true, hi, "hi r6 r7 LSR 29", "hi_r6_r7_LSR_29"},
100 {{ls, r7, r6, LSR, 14}, true, ls, "ls r7 r6 LSR 14", "ls_r7_r6_LSR_14"},
106 {{gt, r6, r4, LSR, 13}, true, gt, "gt r6 r4 LSR 13", "gt_r6_r4_LSR_13"},
107 {{hi, r6, r5, LSR, 12}, true, hi, "hi r6 r5 LSR 12", "hi_r6_r5_LSR_12"},
108 {{pl, r6, r1, ASR, 12}, true, pl, "pl r6 r1 ASR 12", "pl_r6_r1_ASR_12"},
110 {{mi, r7, r6, ASR, 20}, true, mi, "mi r7 r6 ASR 20", "mi_r7_r6_ASR_20"},
111 {{cc, r3, r6, ASR, 22}, true, cc, "cc r3 r6 ASR 22", "cc_r3_r6_ASR_22"},
115 {{pl, r6, r4, ASR, 6}, true, pl, "pl r6 r4 ASR 6", "pl_r6_r4_ASR_6"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc | 97 {{cs, r6, r2, LSL, 8}, true, cs, "cs r6 r2 LSL 8", "cs_r6_r2_LSL_8"},
101 {{ge, r6, r6, LSL, 28}, true, ge, "ge r6 r6 LSL 28", "ge_r6_r6_LSL_28"},
106 {{vs, r6, r0, LSL, 26}, true, vs, "vs r6 r0 LSL 26", "vs_r6_r0_LSL_26"},
116 {{gt, r6, r4, LSL, 23}, true, gt, "gt r6 r4 LSL 23", "gt_r6_r4_LSL_23"},
121 {{le, r6, r6, LSL, 11}, true, le, "le r6 r6 LSL 11", "le_r6_r6_LSL_11"},
124 {{eq, r3, r6, LSL, 12}, true, eq, "eq r3 r6 LSL 12", "eq_r3_r6_LSL_12"},
129 {{vc, r6, r0, LSL, 13}, true, vc, "vc r6 r0 LSL 13", "vc_r6_r0_LSL_13"},
134 {{vc, r5, r6, LSL, 5}, true, vc, "vc r5 r6 LSL 5", "vc_r5_r6_LSL_5"},
135 {{cc, r6, r1, LSL, 14}, true, cc, "cc r6 r1 LSL 14", "cc_r6_r1_LSL_14"},
139 {{eq, r6, r2, LSL, 19}, true, eq, "eq r6 r2 LSL 19", "eq_r6_r2_LSL_19"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc | 102 {{al, r0, r0, LSL, r6}, false, al, "al r0 r0 LSL r6", "al_r0_r0_LSL_r6"},
110 {{al, r0, r0, LSR, r6}, false, al, "al r0 r0 LSR r6", "al_r0_r0_LSR_r6"},
118 {{al, r0, r0, ASR, r6}, false, al, "al r0 r0 ASR r6", "al_r0_r0_ASR_r6"},
126 {{al, r0, r0, ROR, r6}, false, al, "al r0 r0 ROR r6", "al_r0_r0_ROR_r6"},
134 {{al, r1, r1, LSL, r6}, false, al, "al r1 r1 LSL r6", "al_r1_r1_LSL_r6"},
142 {{al, r1, r1, LSR, r6}, false, al, "al r1 r1 LSR r6", "al_r1_r1_LSR_r6"},
150 {{al, r1, r1, ASR, r6}, false, al, "al r1 r1 ASR r6", "al_r1_r1_ASR_r6"},
158 {{al, r1, r1, ROR, r6}, false, al, "al r1 r1 ROR r6", "al_r1_r1_ROR_r6"},
166 {{al, r2, r2, LSL, r6}, false, al, "al r2 r2 LSL r6", "al_r2_r2_LSL_r6"},
174 {{al, r2, r2, LSR, r6}, false, al, "al r2 r2 LSR r6", "al_r2_r2_LSR_r6"},
[all …]
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| D | test-assembler-rd-rn-rm-a32.cc | 109 {{r13, r6, r8}, false, al, "r13 r6 r8", "r13_r6_r8"},
113 {{r6, r0, r7}, false, al, "r6 r0 r7", "r6_r0_r7"},
121 {{r12, r2, r6}, false, al, "r12 r2 r6", "r12_r2_r6"},
124 {{r6, r3, r11}, false, al, "r6 r3 r11", "r6_r3_r11"},
130 {{r6, r5, r7}, false, al, "r6 r5 r7", "r6_r5_r7"},
147 {{r13, r6, r1}, false, al, "r13 r6 r1", "r13_r6_r1"},
148 {{r13, r14, r6}, false, al, "r13 r14 r6", "r13_r14_r6"},
151 {{r1, r6, r13}, false, al, "r1 r6 r13", "r1_r6_r13"},
152 {{r10, r6, r12}, false, al, "r10 r6 r12", "r10_r6_r12"},
158 {{r5, r6, r11}, false, al, "r5 r6 r11", "r5_r6_r11"},
[all …]
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| D | test-assembler-rd-rn-rm-t32.cc | 109 {{r13, r6, r8}, false, al, "r13 r6 r8", "r13_r6_r8"},
113 {{r6, r0, r7}, false, al, "r6 r0 r7", "r6_r0_r7"},
121 {{r12, r2, r6}, false, al, "r12 r2 r6", "r12_r2_r6"},
124 {{r6, r3, r11}, false, al, "r6 r3 r11", "r6_r3_r11"},
130 {{r6, r5, r7}, false, al, "r6 r5 r7", "r6_r5_r7"},
147 {{r13, r6, r1}, false, al, "r13 r6 r1", "r13_r6_r1"},
148 {{r13, r14, r6}, false, al, "r13 r14 r6", "r13_r14_r6"},
151 {{r1, r6, r13}, false, al, "r1 r6 r13", "r1_r6_r13"},
152 {{r10, r6, r12}, false, al, "r10 r6 r12", "r10_r6_r12"},
158 {{r5, r6, r11}, false, al, "r5 r6 r11", "r5_r6_r11"},
[all …]
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| D | test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc | 98 {{ls, r7, r7, r6}, true, ls, "ls r7 r7 r6", "ls_r7_r7_r6"},
101 {{le, r6, r6, r11}, true, le, "le r6 r6 r11", "le_r6_r6_r11"},
129 {{cc, r0, r0, r6}, true, cc, "cc r0 r0 r6", "cc_r0_r0_r6"},
130 {{gt, r4, r4, r6}, true, gt, "gt r4 r4 r6", "gt_r4_r4_r6"},
133 {{vc, r8, r8, r6}, true, vc, "vc r8 r8 r6", "vc_r8_r8_r6"},
142 {{cc, r4, r4, r6}, true, cc, "cc r4 r4 r6", "cc_r4_r4_r6"},
143 {{vc, r6, r6, r14}, true, vc, "vc r6 r6 r14", "vc_r6_r6_r14"},
144 {{hi, r9, r9, r6}, true, hi, "hi r9 r9 r6", "hi_r9_r9_r6"},
161 {{cc, r1, r1, r6}, true, cc, "cc r1 r1 r6", "cc_r1_r1_r6"},
175 {{le, r6, r6, r4}, true, le, "le r6 r6 r4", "le_r6_r6_r4"},
[all …]
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 48 adc r4, r5, r6
50 adc r4, r5, r6, lsl #1
51 adc r4, r5, r6, lsl #31
52 adc r4, r5, r6, lsr #1
53 adc r4, r5, r6, lsr #31
54 adc r4, r5, r6, lsr #32
55 adc r4, r5, r6, asr #1
56 adc r4, r5, r6, asr #31
57 adc r4, r5, r6, asr #32
58 adc r4, r5, r6, ror #1
[all …]
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| /external/libmpeg2/common/arm/ |
| D | impeg2_format_conv.s | 139 mov r6, r5
145 sub r6, r6, #16
146 cmp r6, #15
149 cmp r6, #0
155 rsb r6, r6, #16
156 sub r0, r0, r6
157 sub r3, r3, r6
189 mov r6, r5
198 sub r6, r6, #8
199 cmp r6, #7
[all …]
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| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 31 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
33 ldmia r0,{r3,r4,r5,r6,r7}
39 mov r6,r6,ror#30
49 eor r10,r5,r6 @ F_xx_xx
56 eor r10,r5,r6 @ F_xx_xx
64 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
71 add r6,r8,r6,ror#2 @ E+=K_00_19
76 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
80 add r6,r8,r6,ror#2 @ E+=K_00_19
82 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
[all …]
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| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 32 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
34 ldmia r0,{r3,r4,r5,r6,r7}
40 mov r6,r6,ror#30
50 eor r10,r5,r6 @ F_xx_xx
57 eor r10,r5,r6 @ F_xx_xx
65 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
72 add r6,r8,r6,ror#2 @ E+=K_00_19
77 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
81 add r6,r8,r6,ror#2 @ E+=K_00_19
83 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
[all …]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 68 adc r4, r5, r6
70 adc r4, r5, r6, lsl #1
71 adc r4, r5, r6, lsl #31
72 adc r4, r5, r6, lsr #1
73 adc r4, r5, r6, lsr #31
74 adc r4, r5, r6, lsr #32
75 adc r4, r5, r6, asr #1
76 adc r4, r5, r6, asr #31
77 adc r4, r5, r6, asr #32
78 adc r4, r5, r6, ror #1
[all …]
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| /external/compiler-rt/lib/tsan/rtl/ |
| D | tsan_rtl_ppc64.S | 54 ld r6,-28696(r13)
56 xor r5,r6,r5
60 xor r0,r6,r0
104 addi r6,r5,16
107 stvx v21,0,r6
108 addi r6,r6,32
111 stvx v23,0,r6
112 addi r6,r6,32
115 stvx v25,0,r6
116 addi r6,r6,32
[all …]
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| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_420p.s | 97 @ LDR r6,[sp,#56] @//Load u2_strideuv
113 MOV r6,r8 @// Copying width
117 SUB r6,r6,#16
120 CMP r6,#16
122 CMP r6,#0
128 RSB r6,r6,#16
129 SUB r0,r0,r6
130 SUB r2,r2,r6
164 MOV r6,r8 @// Copying width
168 SUB r6,r6,#16
[all …]
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| /external/tremolo/Tremolo/ |
| D | mdctARM.s | 63 LDMDB r2!,{r5,r6,r7,r12}
66 MOV r6, r6, ASR #9 @ r6 = (*--r)>>9
80 MOV r14,r6, ASR #15
82 EORNE r6, r4, r14,ASR #31
83 STRH r6, [r0], r3
125 LDR r6, [r2],#8
130 RSB r6, r6, #0
135 MOV r6, r6, ASR #9 @ r6 = (-*l)>>9
148 MOV r14,r6, ASR #15
150 EORNE r6, r4, r14,ASR #31
[all …]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 37 # CHECK: adc r4, r5, r6
39 # CHECK: adc r4, r5, r6, lsl #1
40 # CHECK: adc r4, r5, r6, lsl #31
41 # CHECK: adc r4, r5, r6, lsr #1
42 # CHECK: adc r4, r5, r6, lsr #31
43 # CHECK: adc r4, r5, r6, lsr #32
44 # CHECK: adc r4, r5, r6, asr #1
45 # CHECK: adc r4, r5, r6, asr #31
46 # CHECK: adc r4, r5, r6, asr #32
47 # CHECK: adc r4, r5, r6, ror #1
[all …]
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