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Searched refs:ra_reg_count (Results 1 – 3 of 3) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_vec4_reg_allocate.cpp108 int ra_reg_count = 0; in brw_vec4_alloc_reg_set() local
110 ra_reg_count += base_reg_count - (class_sizes[i] - 1); in brw_vec4_alloc_reg_set()
114 compiler->vec4_reg_set.ra_reg_to_grf = ralloc_array(compiler, uint8_t, ra_reg_count); in brw_vec4_alloc_reg_set()
116 compiler->vec4_reg_set.regs = ra_alloc_reg_set(compiler, ra_reg_count, false); in brw_vec4_alloc_reg_set()
157 assert(reg == ra_reg_count); in brw_vec4_alloc_reg_set()
Dbrw_fs_reg_allocate.cpp116 int ra_reg_count = 0; in brw_alloc_reg_set() local
129 ra_reg_count += (base_reg_count - (class_sizes[i] - 1)) / 2; in brw_alloc_reg_set()
131 ra_reg_count += base_reg_count - (class_sizes[i] - 1); in brw_alloc_reg_set()
134 class_to_ra_reg_range[class_sizes[i]] = ra_reg_count; in brw_alloc_reg_set()
143 uint8_t *ra_reg_to_grf = ralloc_array(compiler, uint8_t, ra_reg_count); in brw_alloc_reg_set()
144 struct ra_regs *regs = ra_alloc_reg_set(compiler, ra_reg_count, false); in brw_alloc_reg_set()
241 assert(reg == ra_reg_count); in brw_alloc_reg_set()
/external/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3_ra.c138 unsigned ra_reg_count, reg, first_half_reg; in ir3_ra_alloc_reg_set() local
142 ra_reg_count = 0; in ir3_ra_alloc_reg_set()
144 ra_reg_count += CLASS_REGS(i); in ir3_ra_alloc_reg_set()
146 ra_reg_count += HALF_CLASS_REGS(i); in ir3_ra_alloc_reg_set()
193 set->regs = ra_alloc_reg_set(set, ra_reg_count, true); in ir3_ra_alloc_reg_set()
194 set->ra_reg_to_gpr = ralloc_array(set, uint16_t, ra_reg_count); in ir3_ra_alloc_reg_set()