| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vecFold.ll | 80 define <8 x i16> @raddhn(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readn…
81 ; CHECK-LABEL: raddhn:
83 ; CHECK: raddhn.4h v0, v0, v1
86 …%vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) no…
87 …%vraddhn2.i10 = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) …
142 declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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| D | arm64-vadd.ll | 67 ;CHECK: raddhn.8b
70 %tmp3 = call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
76 ;CHECK: raddhn.4h
79 %tmp3 = call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
85 ;CHECK: raddhn.2s
88 %tmp3 = call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
94 ;CHECK: raddhn.8b
96 …%vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwi…
97 …%vraddhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b) n…
104 ;CHECK: raddhn.4h
[all …]
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| D | arm64-neon-3vdiff.ll | 47 declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>)
49 declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>)
51 declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>)
691 ; CHECK: raddhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
693 %vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)
699 ; CHECK: raddhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
701 %vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)
707 ; CHECK: raddhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
709 %vraddhn2.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)
715 ; CHECK: raddhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-3vdiff.s | 385 raddhn v0.8b, v1.8h, v2.8h
386 raddhn v0.4h, v1.4s, v2.4s
387 raddhn v0.2s, v1.2d, v2.2d
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| D | neon-diagnostics.s | 2791 raddhn v0.8b, v1.8h, v2.8b
2792 raddhn v0.4h, v1.4s, v2.4h
2793 raddhn v0.2s, v1.2d, v2.2s
|
| /external/libmpeg2/common/armv8/ |
| D | impeg2_idct.s | 242 raddhn v12.4h, v0.4s, v8.4s
252 raddhn v12.4h, v0.4s, v8.4s
262 raddhn v12.4h, v0.4s, v8.4s
272 raddhn v12.4h, v0.4s, v8.4s
282 raddhn v12.4h, v0.4s, v8.4s
292 raddhn v12.4h, v0.4s, v8.4s
302 raddhn v12.4h, v0.4s, v8.4s
312 raddhn v12.4h, v0.4s, v8.4s
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 1444 # CHECK: raddhn v0.8b, v1.8h, v2.8h
1445 # CHECK: raddhn v0.4h, v1.4s, v2.4s
1446 # CHECK: raddhn v0.2s, v1.2d, v2.2d
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.c | 2728 GEN_BINARY_TEST(raddhn, 2s, 2d, 2d)
2730 GEN_BINARY_TEST(raddhn, 4h, 4s, 4s)
2732 GEN_BINARY_TEST(raddhn, 8b, 8h, 8h)
|
| D | fp_and_simd.stdout.exp | 26959 raddhn v9.2s, v7.2d, v8.2d afbfc85e0c1c48334ea1524a0ade5200 79487a40a5dfbc0cb0537f133e68f917 000…
26961 raddhn v9.4h, v7.4s, v8.4s df28535a766ecc147823af2632098729 6a45a6db9a685742f5028d2d94cc5d5a 000…
26963 raddhn v9.8b, v7.8h, v8.8h a51d242dcced68587d6bcf2a3b0a82f7 86fd3e4bb26cd1f8ebe5c4ab42948c9f 000…
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1318 __ raddhn(v22.V2S(), v10.V2D(), v21.V2D()); in GenerateTestSequenceNEON() local
1319 __ raddhn(v5.V4H(), v13.V4S(), v13.V4S()); in GenerateTestSequenceNEON() local
1320 __ raddhn(v10.V8B(), v17.V8H(), v26.V8H()); in GenerateTestSequenceNEON() local
|
| D | test-simulator-aarch64.cc | 4207 DEFINE_TEST_NEON_3DIFF_NARROW(raddhn, Basic)
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 1084 0x~~~~~~~~~~~~~~~~ 2eb54156 raddhn v22.2s, v10.2d, v21.2d
1085 0x~~~~~~~~~~~~~~~~ 2e6d41a5 raddhn v5.4h, v13.4s, v13.4s
1086 0x~~~~~~~~~~~~~~~~ 2e3a422a raddhn v10.8b, v17.8h, v26.8h
|
| D | log-disasm-colour | 1084 0x~~~~~~~~~~~~~~~~ 2eb54156 raddhn v22.2s, v10.2d, v21.2d
1085 0x~~~~~~~~~~~~~~~~ 2e6d41a5 raddhn v5.4h, v13.4s, v13.4s
1086 0x~~~~~~~~~~~~~~~~ 2e3a422a raddhn v10.8b, v17.8h, v26.8h
|
| D | log-all | 2991 0x~~~~~~~~~~~~~~~~ 2eb54156 raddhn v22.2s, v10.2d, v21.2d
2993 0x~~~~~~~~~~~~~~~~ 2e6d41a5 raddhn v5.4h, v13.4s, v13.4s
2995 0x~~~~~~~~~~~~~~~~ 2e3a422a raddhn v10.8b, v17.8h, v26.8h
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2439 void raddhn(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| D | simulator-aarch64.h | 2662 V(raddhn) \
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| D | macro-assembler-aarch64.h | 2163 V(raddhn, Raddhn) \
|
| D | simulator-aarch64.cc | 3658 raddhn(vf, rd, rn, rm); in VisitNEON3Different()
|
| D | logic-aarch64.cc | 3387 LogicVRegister Simulator::raddhn(VectorFormat vform, in raddhn() function in vixl::aarch64::Simulator
|
| D | assembler-aarch64.cc | 1950 V(raddhn, NEON_RADDHN, vd.IsD()) \
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2860 void raddhn(const VRegister& vd,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3535 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 246 aarch64_neon_raddhn, // llvm.aarch64.neon.raddhn
6304 "llvm.aarch64.neon.raddhn",
14244 1, // llvm.aarch64.neon.raddhn
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 238 aarch64_neon_raddhn, // llvm.aarch64.neon.raddhn
6262 "llvm.aarch64.neon.raddhn",
14147 1, // llvm.aarch64.neon.raddhn
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 246 aarch64_neon_raddhn, // llvm.aarch64.neon.raddhn
6304 "llvm.aarch64.neon.raddhn",
14244 1, // llvm.aarch64.neon.raddhn
|