/external/fio/engines/ |
D | rdma.c | 194 struct rdmaio_data *rd = td->io_ops_data; in client_recv() local 197 if (wc->byte_len != sizeof(rd->recv_buf)) { in client_recv() 203 if (max_bs > ntohl(rd->recv_buf.max_bs)) { in client_recv() 206 ntohl(rd->recv_buf.max_bs), max_bs); in client_recv() 211 if ((rd->rdma_protocol == FIO_RDMA_MEM_WRITE) || in client_recv() 212 (rd->rdma_protocol == FIO_RDMA_MEM_READ)) { in client_recv() 216 rd->rmt_nr = ntohl(rd->recv_buf.nr); in client_recv() 218 for (i = 0; i < rd->rmt_nr; i++) { in client_recv() 219 rd->rmt_us[i].buf = ntohll(rd->recv_buf.rmt_us[i].buf); in client_recv() 220 rd->rmt_us[i].rkey = ntohl(rd->recv_buf.rmt_us[i].rkey); in client_recv() [all …]
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/external/valgrind/none/tests/mips64/ |
D | cvm_atomic.stdout.exp-BE | 1 baddu $t3, $t1, $t2 :: rd 0x4, rs 0x42b0c0a28677b502, rt 0x42b0c0a28677b502 2 baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x42b0c0a28677b502, rt 0x9e705cc51ad8dca0 3 baddu $t3, $t1, $t2 :: rd 0x82, rs 0x42b0c0a28677b502, rt 0x47f505569a08a180 4 baddu $t3, $t1, $t2 :: rd 0x99, rs 0x42b0c0a28677b502, rt 0x94ff52fc81afa797 5 baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x42b0c0a28677b502, rt 0x556b3ecaccf17ac5 6 baddu $t3, $t1, $t2 :: rd 0x68, rs 0x42b0c0a28677b502, rt 0x3c2cd9a9cda20766 7 baddu $t3, $t1, $t2 :: rd 0x38, rs 0x42b0c0a28677b502, rt 0xd0d070db710cd036 8 baddu $t3, $t1, $t2 :: rd 0xa9, rs 0x42b0c0a28677b502, rt 0x2f39454412d6e4a7 9 baddu $t3, $t1, $t2 :: rd 0x16, rs 0x42b0c0a28677b502, rt 0xed5005cbc8b0a214 10 baddu $t3, $t1, $t2 :: rd 0x42, rs 0x42b0c0a28677b502, rt 0x87750a04ad765040 [all …]
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D | cvm_atomic.stdout.exp-LE | 1 baddu $t3, $t1, $t2 :: rd 0x4, rs 0x42b0c0a28677b502, rt 0x42b0c0a28677b502 2 baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x42b0c0a28677b502, rt 0x9e705cc51ad8dca0 3 baddu $t3, $t1, $t2 :: rd 0x82, rs 0x42b0c0a28677b502, rt 0x47f505569a08a180 4 baddu $t3, $t1, $t2 :: rd 0x99, rs 0x42b0c0a28677b502, rt 0x94ff52fc81afa797 5 baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x42b0c0a28677b502, rt 0x556b3ecaccf17ac5 6 baddu $t3, $t1, $t2 :: rd 0x68, rs 0x42b0c0a28677b502, rt 0x3c2cd9a9cda20766 7 baddu $t3, $t1, $t2 :: rd 0x38, rs 0x42b0c0a28677b502, rt 0xd0d070db710cd036 8 baddu $t3, $t1, $t2 :: rd 0xa9, rs 0x42b0c0a28677b502, rt 0x2f39454412d6e4a7 9 baddu $t3, $t1, $t2 :: rd 0x16, rs 0x42b0c0a28677b502, rt 0xed5005cbc8b0a214 10 baddu $t3, $t1, $t2 :: rd 0x42, rs 0x42b0c0a28677b502, rt 0x87750a04ad765040 [all …]
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D | cvm_ins.stdout.exp | 514 sne $t1, $t2 ,$t3 :: rd 0x0 rs 0x0, rt 0x0 515 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x130476dc 516 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x2608edb8 517 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x350c9b64 518 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x4c11db70 519 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x5f15adac 520 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x6a1936c8 521 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x791d4014 522 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x9823b6e0 523 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x8b27c03c [all …]
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 233 Register rd, 237 Register rd, 239 typedef void (Assembler::*InstructionROp)(Register rd, 242 Register rd, 247 Register rd, 253 Register rd, 257 Register rd, 267 Register rd, 274 Register rd, 311 Condition cond, Register rd, Register rn, Register rm, Register ra); [all …]
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D | macro-assembler-aarch32.h | 749 void Adr(Condition cond, Register rd, RawLiteral* literal) { in Adr() argument 750 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); in Adr() 753 EmitLiteralCondRL<&Assembler::adr> emit_helper(rd); in Adr() 756 void Adr(Register rd, RawLiteral* literal) { Adr(al, rd, literal); } in Adr() argument 817 void Vldr(Condition cond, DataType dt, DRegister rd, RawLiteral* literal) { in Vldr() argument 818 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); in Vldr() 821 EmitLiteralCondDtDL<&Assembler::vldr> emit_helper(dt, rd); in Vldr() 824 void Vldr(DataType dt, DRegister rd, RawLiteral* literal) { in Vldr() argument 825 Vldr(al, dt, rd, literal); in Vldr() 827 void Vldr(Condition cond, DRegister rd, RawLiteral* literal) { in Vldr() argument [all …]
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D | disasm-aarch32.h | 480 Register rd, 486 Register rd, 492 Register rd, 496 void add(Condition cond, Register rd, const Operand& operand); 500 Register rd, 504 void adds(Register rd, const Operand& operand); 506 void addw(Condition cond, Register rd, Register rn, const Operand& operand); 508 void adr(Condition cond, EncodingSize size, Register rd, Label* label); 512 Register rd, 518 Register rd, [all …]
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D | disasm-aarch32.cc | 1118 Register rd, in adc() argument 1124 if (!rd.Is(rn)) { in adc() 1125 os() << rd << ", "; in adc() 1132 Register rd, in adcs() argument 1138 if (!rd.Is(rn)) { in adcs() 1139 os() << rd << ", "; in adcs() 1146 Register rd, in add() argument 1152 if (!rd.Is(rn)) { in add() 1153 os() << rd << ", "; in add() 1158 void Disassembler::add(Condition cond, Register rd, const Operand& operand) { in add() argument [all …]
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D | assembler-aarch32.cc | 1800 Register rd, in adc() argument 1811 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in adc() 1812 EmitT32_32(0xf1400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adc() 1824 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in adc() 1835 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in adc() 1837 EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3)); in adc() 1848 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in adc() 1850 EmitT32_32(0xeb400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adc() 1861 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adc() 1872 if (cond.IsNotNever() && ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && in adc() [all …]
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/external/v8/src/arm64/ |
D | macro-assembler-arm64-inl.h | 46 void MacroAssembler::And(const Register& rd, in And() argument 50 DCHECK(!rd.IsZero()); in And() 51 LogicalMacro(rd, rn, operand, AND); in And() 55 void MacroAssembler::Ands(const Register& rd, in Ands() argument 59 DCHECK(!rd.IsZero()); in Ands() 60 LogicalMacro(rd, rn, operand, ANDS); in Ands() 71 void MacroAssembler::Bic(const Register& rd, in Bic() argument 75 DCHECK(!rd.IsZero()); in Bic() 76 LogicalMacro(rd, rn, operand, BIC); in Bic() 80 void MacroAssembler::Bics(const Register& rd, in Bics() argument [all …]
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D | assembler-arm64.cc | 1082 void Assembler::adr(const Register& rd, int imm21) { in adr() argument 1083 DCHECK(rd.Is64Bits()); in adr() 1084 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr() 1088 void Assembler::adr(const Register& rd, Label* label) { in adr() argument 1089 adr(rd, LinkAndGetByteOffsetTo(label)); in adr() 1093 void Assembler::add(const Register& rd, in add() argument 1096 AddSub(rd, rn, operand, LeaveFlags, ADD); in add() 1100 void Assembler::adds(const Register& rd, in adds() argument 1103 AddSub(rd, rn, operand, SetFlags, ADD); in adds() 1114 void Assembler::sub(const Register& rd, in sub() argument [all …]
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D | assembler-arm64.h | 1013 void adr(const Register& rd, Label* label); 1014 void adr(const Register& rd, int imm21); 1018 void add(const Register& rd, 1023 void adds(const Register& rd, 1031 void sub(const Register& rd, 1036 void subs(const Register& rd, 1044 void neg(const Register& rd, 1048 void negs(const Register& rd, 1052 void adc(const Register& rd, 1057 void adcs(const Register& rd, [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcInstrAliases.td | 15 // mov<cond> <ccreg> rs2, rd 20 // mov<cond> (%icc|%xcc), rs2, rd 22 ", $rs2, $rd"), 23 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>; 25 // mov<cond> (%icc|%xcc), simm11, rd 27 ", $simm11, $rd"), 28 (movri IntRegs:$rd, i32imm:$simm11, condVal)>; 30 // fmovs<cond> (%icc|%xcc), $rs2, $rd 32 ", $rs2, $rd"), 33 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>; [all …]
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D | SparcInstrVIS.td | 21 (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 22 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 27 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 28 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 31 let rd = 0, rs1 = 0, rs2 = 0 in 35 // For VIS Instructions with only rs1, rd operands. 39 (outs RC:$rd), (ins RC:$rs1), 40 !strconcat(OpcStr, " $rs1, $rd"), []>; 42 // For VIS Instructions with only rs2, rd operands. 46 (outs RC:$rd), (ins RC:$rs2), [all …]
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D | SparcInstrInfo.td | 292 (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 293 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 294 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))], 297 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13), 298 !strconcat(OpcStr, " $rs1, $simm13, $rd"), 299 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))], 307 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 308 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [], 311 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 312 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [], [all …]
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/external/valgrind/none/tests/arm64/ |
D | crc32.stdout.exp | 2 crc32b w21,w20,w19 :: rd 00000000f8957d4c rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 000… 3 crc32b w21,w20,w19 :: rd 00000000f810b326 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 000… 4 crc32b w21,w20,w19 :: rd 00000000ef405c96 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 000… 5 crc32b w21,w20,w19 :: rd 00000000a0db523c rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 000… 6 crc32b w21,w20,w19 :: rd 0000000096de687b rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 000… 7 crc32b w21,w20,w19 :: rd 000000005b546bd0 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 000… 8 crc32b w21,w20,w19 :: rd 000000008f7a8684 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 000… 9 crc32h w21,w20,w19 :: rd 00000000862b47a9 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 000… 10 crc32h w21,w20,w19 :: rd 000000009a47a305 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 000… 11 crc32h w21,w20,w19 :: rd 00000000a788663d rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 000… [all …]
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D | integer.stdout.exp | 2 add x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000… 3 add w3, w4, w5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000… 4 adc x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000… 5 adc x3, x4, x5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 2000000… 6 adc x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 0000000… 7 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 2000000… 8 adc x3, x4, x5 :: rd 5859704f00000000 rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 0000000… 9 adc x3, x4, x5 :: rd 5859704f00000001 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 2000000… 10 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 0000000… 11 adc x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 2000000… [all …]
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/external/valgrind/none/tests/mips32/ |
D | MIPS32int.stdout.exp-mips32-LE | 2 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000 3 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001 4 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000 5 add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001 6 add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff 7 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff 8 add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000 9 add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728 10 add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728 11 add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000 [all …]
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D | MIPS32int.stdout.exp-mips32-BE | 2 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000 3 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001 4 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000 5 add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001 6 add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff 7 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff 8 add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000 9 add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728 10 add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728 11 add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000 [all …]
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D | MIPS32int.stdout.exp-mips32r2-BE | 2 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000 3 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001 4 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000 5 add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001 6 add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff 7 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff 8 add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000 9 add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728 10 add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728 11 add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000 [all …]
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D | MIPS32int.stdout.exp-mips32r2-LE | 2 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000 3 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001 4 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000 5 add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001 6 add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff 7 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff 8 add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000 9 add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728 10 add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728 11 add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000 [all …]
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/external/valgrind/none/tests/arm/ |
D | v6intARM.stdout.exp | 2 mov r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 3 cpy r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 6 movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 7 movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000 Z 8 movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 0, cpsr 0x80000000 N 11 movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000 C 12 movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 1, cpsr 0x60000000 ZC 13 movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 1, cpsr 0xa0000000 N C 17 mvn r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x00000000 18 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x80000000 N [all …]
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D | v6media.stdout.exp | 2 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[… 3 mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[… 4 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[… 5 mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[… 6 mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[… 7 mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[… 9 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x… 10 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x… 11 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x… 12 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x… [all …]
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/external/vixl/src/aarch64/ |
D | simulator-aarch64.cc | 2624 SimVRegister& rd = ReadVRegister(instr->GetRd()); in VisitFPDataProcessing1Source() local 2670 fsqrt(vform, rd, rn); in VisitFPDataProcessing1Source() 2706 frint(vform, rd, rn, fpcr_rounding, inexact_exception); in VisitFPDataProcessing1Source() 2716 SimVRegister& rd = ReadVRegister(instr->GetRd()); in VisitFPDataProcessing2Source() local 2723 fadd(vform, rd, rn, rm); in VisitFPDataProcessing2Source() 2727 fsub(vform, rd, rn, rm); in VisitFPDataProcessing2Source() 2731 fmul(vform, rd, rn, rm); in VisitFPDataProcessing2Source() 2735 fnmul(vform, rd, rn, rm); in VisitFPDataProcessing2Source() 2739 fdiv(vform, rd, rn, rm); in VisitFPDataProcessing2Source() 2743 fmax(vform, rd, rn, rm); in VisitFPDataProcessing2Source() [all …]
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/external/icu/icu4c/source/test/cintltst/ |
D | uregiontest.c | 362 const KnownRegion * rd; in TestKnownRegions() local 363 for (rd = knownRegions; rd->code != NULL ; rd++ ) { in TestKnownRegions() 365 const URegion *r = uregion_getRegionFromCode(rd->code, &status); in TestKnownRegions() 368 int32_t e = rd->numeric; in TestKnownRegions() 372 if (uregion_getType(r) != rd->type) { in TestKnownRegions() 373 …Expected region %s to be of type %d. Got: %d\n", uregion_getRegionCode(r), rd->type, uregion_getTy… in TestKnownRegions() 383 log_data_err("ERROR: Known region %s was not recognized.\n", rd->code); in TestKnownRegions() 389 const KnownRegion * rd; in TestGetContainedRegions() local 390 for (rd = knownRegions; rd->code != NULL ; rd++ ) { in TestGetContainedRegions() 392 const URegion *r = uregion_getRegionFromCode(rd->code, &status); in TestGetContainedRegions() [all …]
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