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/external/linux-kselftest/tools/testing/selftests/powerpc/include/
Dvmx_asm.h13 #define PUSH_VMX(pos,reg) \ argument
14 li reg,pos; \
15 stvx v20,reg,%r1; \
16 addi reg,reg,16; \
17 stvx v21,reg,%r1; \
18 addi reg,reg,16; \
19 stvx v22,reg,%r1; \
20 addi reg,reg,16; \
21 stvx v23,reg,%r1; \
22 addi reg,reg,16; \
[all …]
/external/gemmlowp/internal/
Dsimd_wrappers_common_neon_sse.h32 result.buf.reg[i] = LoadInt32x4(src.data(row, col + i));
46 result.buf.reg[2 * i + 0] = LoadInt32x4(src.data(row + 0, col + i));
47 result.buf.reg[2 * i + 1] = LoadInt32x4(src.data(row + 4, col + i));
64 result.buf.reg[0] = LoadInt32x4(buf);
80 result.buf.reg[0] = LoadInt32x4(buf);
81 result.buf.reg[1] = LoadInt32x4(buf + 4);
92 result.buf.reg[0] = LoadInt32x4(src.data(pos));
103 result.buf.reg[0] = LoadInt32x4(src(0));
120 result.buf.reg[0] = LoadInt32x4(src.data(pos));
137 result.buf.reg[0] = LoadInt32x4(src.data(pos));
[all …]
Doutput_sse.h38 __m128i res_16 = _mm_packs_epi32(input.reg[0], input.reg[0]);
40 output.reg[0] = _mm_cvtsi128_si32(res_8);
57 __m128i res_16 = _mm_packs_epi32(input.reg[0], input.reg[1]);
59 output.reg[0] = _mm_extract_epi32(res_8, 0);
60 output.reg[1] = _mm_extract_epi32(res_8, 1);
77 __m128i res_16_0 = _mm_packs_epi32(input.reg[0], input.reg[1]);
78 __m128i res_16_1 = _mm_packs_epi32(input.reg[2], input.reg[3]);
79 output.reg[0] = _mm_packus_epi16(res_16_0, res_16_1);
96 __m128i res_16_0 = _mm_packs_epi32(input.reg[0], input.reg[1]);
97 __m128i res_16_1 = _mm_packs_epi32(input.reg[2], input.reg[3]);
[all …]
Doutput_neon.h38 int16x4_t res_16 = vqmovn_s32(input.reg[0]);
40 output.reg[0] = vget_lane_u32(vreinterpret_u32_u8(res_8), 0);
58 vcombine_s16(vqmovn_s32(input.reg[0]), vqmovn_s32(input.reg[1]));
59 output.reg[0] = vqmovun_s16(res_16);
77 vcombine_s16(vqmovn_s32(input.reg[0]), vqmovn_s32(input.reg[1]));
79 vcombine_s16(vqmovn_s32(input.reg[2]), vqmovn_s32(input.reg[3]));
80 output.reg[0] = vqmovun_s16(res_16_0);
81 output.reg[1] = vqmovun_s16(res_16_1);
100 res_16[i] = vcombine_s16(vqmovn_s32(input.reg[2 * i]),
101 vqmovn_s32(input.reg[2 * i + 1]));
[all …]
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_ir_fs.h39 fs_reg(struct ::brw_reg reg);
57 negate(fs_reg reg) in negate() argument
59 assert(reg.file != IMM); in negate()
60 reg.negate = !reg.negate; in negate()
61 return reg; in negate()
65 retype(fs_reg reg, enum brw_reg_type type) in retype() argument
67 reg.type = type; in retype()
68 return reg; in retype()
72 byte_offset(fs_reg reg, unsigned delta) in byte_offset() argument
74 switch (reg.file) { in byte_offset()
[all …]
Dbrw_ir_vec4.h44 src_reg(struct ::brw_reg reg);
51 explicit src_reg(const dst_reg &reg);
57 retype(src_reg reg, enum brw_reg_type type) in retype() argument
59 reg.type = type; in retype()
60 return reg; in retype()
66 add_byte_offset(backend_reg *reg, unsigned bytes) in add_byte_offset() argument
68 switch (reg->file) { in add_byte_offset()
74 reg->offset += bytes; in add_byte_offset()
75 assert(reg->offset % 16 == 0); in add_byte_offset()
78 const unsigned suboffset = reg->offset + bytes; in add_byte_offset()
[all …]
Dbrw_clip_line.c52 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_clip_line_alloc_regs()
55 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
67 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
71 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_line_alloc_regs()
72 c->reg.t0 = brw_vec1_grf(i, 1); in brw_clip_line_alloc_regs()
73 c->reg.t1 = brw_vec1_grf(i, 2); in brw_clip_line_alloc_regs()
74 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_line_alloc_regs()
75 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_line_alloc_regs()
78 c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_line_alloc_regs()
79 c->reg.dp1 = brw_vec1_grf(i, 4); in brw_clip_line_alloc_regs()
[all …]
Dbrw_reg.h366 struct brw_reg reg; in brw_reg() local
376 reg.type = type; in brw_reg()
377 reg.file = file; in brw_reg()
378 reg.negate = negate; in brw_reg()
379 reg.abs = abs; in brw_reg()
380 reg.address_mode = BRW_ADDRESS_DIRECT; in brw_reg()
381 reg.pad0 = 0; in brw_reg()
382 reg.subnr = subnr * type_sz(type); in brw_reg()
383 reg.nr = nr; in brw_reg()
391 reg.swizzle = swizzle; in brw_reg()
[all …]
Dbrw_ff_gs_emit.c62 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_ff_gs_alloc_regs()
66 c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_ff_gs_alloc_regs()
71 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_ff_gs_alloc_regs()
75 c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_ff_gs_alloc_regs()
76 c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_ff_gs_alloc_regs()
79 c->reg.destination_indices = in brw_ff_gs_alloc_regs()
105 brw_MOV(p, c->reg.header, c->reg.R0); in brw_ff_gs_initialize_header()
119 brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2)); in brw_ff_gs_overwrite_header_dw2()
133 brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2), in brw_ff_gs_overwrite_header_dw2_from_r0()
135 brw_SHL(p, get_element_ud(c->reg.header, 2), in brw_ff_gs_overwrite_header_dw2_from_r0()
[all …]
Dbrw_clip_tri.c57 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_clip_tri_alloc_regs()
60 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
72 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
83 brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0)); in brw_clip_tri_alloc_regs()
87 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_tri_alloc_regs()
88 c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D); in brw_clip_tri_alloc_regs()
89 c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs()
90 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs()
91 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_tri_alloc_regs()
94 c->reg.dpPrev = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_tri_alloc_regs()
[all …]
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_sanity.c67 scan_register_key(const scan_register *reg) in scan_register_key() argument
69 unsigned key = reg->file; in scan_register_key()
70 key |= (reg->indices[0] << 4); in scan_register_key()
71 key |= (reg->indices[1] << 18); in scan_register_key()
77 fill_scan_register1d(scan_register *reg, in fill_scan_register1d() argument
80 reg->file = file; in fill_scan_register1d()
81 reg->dimensions = 1; in fill_scan_register1d()
82 reg->indices[0] = index; in fill_scan_register1d()
83 reg->indices[1] = 0; in fill_scan_register1d()
87 fill_scan_register2d(scan_register *reg, in fill_scan_register2d() argument
[all …]
/external/syslinux/gpxe/src/drivers/net/e1000/
De1000_osdep.h78 #define E1000_WRITE_REG(a, reg, value) \ argument
80 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))
82 #define E1000_READ_REG(a, reg) \ argument
84 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))
86 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ argument
88 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
91 #define E1000_READ_REG_ARRAY(a, reg, offset) \ argument
93 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
99 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) \ argument
101 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
[all …]
/external/mesa3d/src/amd/vulkan/
Dradv_cs.h42 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned nu… in radeon_set_config_reg_seq() argument
44 assert(reg < R600_CONTEXT_REG_OFFSET); in radeon_set_config_reg_seq()
47 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
50 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_config_reg() argument
52 radeon_set_config_reg_seq(cs, reg, 1); in radeon_set_config_reg()
56 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned n… in radeon_set_context_reg_seq() argument
58 assert(reg >= R600_CONTEXT_REG_OFFSET); in radeon_set_context_reg_seq()
61 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
64 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_context_reg() argument
66 radeon_set_context_reg_seq(cs, reg, 1); in radeon_set_context_reg()
[all …]
/external/mesa3d/src/mesa/drivers/dri/i915/
Di915_program.c42 #define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
43 #define D0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
44 #define T0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
45 #define A0_SRC0( reg ) (((reg)&UREG_MASK)>>UREG_A0_SRC0_SHIFT_LEFT) argument
46 #define A1_SRC0( reg ) (((reg)&UREG_MASK)<<UREG_A1_SRC0_SHIFT_RIGHT) argument
47 #define A1_SRC1( reg ) (((reg)&UREG_MASK)>>UREG_A1_SRC1_SHIFT_LEFT) argument
48 #define A2_SRC1( reg ) (((reg)&UREG_MASK)<<UREG_A2_SRC1_SHIFT_RIGHT) argument
49 #define A2_SRC2( reg ) (((reg)&UREG_MASK)>>UREG_A2_SRC2_SHIFT_LEFT) argument
53 #define T0_SAMPLER( reg ) (GET_UREG_NR(reg)<<T0_SAMPLER_NR_SHIFT) argument
54 #define T1_ADDRESS_REG( reg ) ((GET_UREG_NR(reg)<<T1_ADDRESS_REG_NR_SHIFT) | \ argument
[all …]
/external/mesa3d/src/compiler/nir/
Dnir_lower_regs_to_ssa.c48 nir_register *reg = src->reg.reg; in rewrite_src() local
49 struct nir_phi_builder_value *value = state->values[reg->index]; in rewrite_src()
74 nir_register *reg = nif->condition.reg.reg; in rewrite_if_condition() local
75 struct nir_phi_builder_value *value = state->values[reg->index]; in rewrite_if_condition()
91 nir_instr *instr = dest->reg.parent_instr; in rewrite_dest()
92 nir_register *reg = dest->reg.reg; in rewrite_dest() local
93 struct nir_phi_builder_value *value = state->values[reg->index]; in rewrite_dest()
97 list_del(&dest->reg.def_link); in rewrite_dest()
98 nir_ssa_dest_init(instr, dest, reg->num_components, in rewrite_dest()
99 reg->bit_size, reg->name); in rewrite_dest()
[all …]
/external/mesa3d/src/gallium/drivers/i915/
Di915_fpc_emit.c48 i915_release_temp(struct i915_fp_compile *p, int reg) in i915_release_temp() argument
50 p->temp_flag &= ~(1 << reg); in i915_release_temp()
82 uint reg = UREG(type, nr); in i915_emit_decl() local
86 return reg; in i915_emit_decl()
92 return reg; in i915_emit_decl()
97 return reg; in i915_emit_decl()
100 *(p->decl++) = (D0_DCL | D0_DEST(reg) | d0_flags); in i915_emit_decl()
108 return reg; in i915_emit_decl()
286 unsigned reg, idx; in i915_emit_const1f() local
293 for (reg = 0; reg < I915_MAX_CONSTANT; reg++) { in i915_emit_const1f()
[all …]
Di915_fpc.h127 #define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20)) argument
130 #define GET_UREG_TYPE(reg) (((reg)>>UREG_TYPE_SHIFT)&REG_TYPE_MASK) argument
131 #define GET_UREG_NR(reg) (((reg)>>UREG_NR_SHIFT)&REG_NR_MASK) argument
140 swizzle(int reg, uint x, uint y, uint z, uint w) in swizzle() argument
146 return ((reg & ~UREG_XYZW_CHANNEL_MASK) | in swizzle()
147 CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) | in swizzle()
148 CHANNEL_SRC(GET_CHANNEL_SRC(reg, y), 1) | in swizzle()
149 CHANNEL_SRC(GET_CHANNEL_SRC(reg, z), 2) | in swizzle()
150 CHANNEL_SRC(GET_CHANNEL_SRC(reg, w), 3)); in swizzle()
154 #define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
[all …]
/external/libunwind/src/x86_64/
DGstash_frame.c37 rs->reg[DWARF_CFA_REG_COLUMN].where, in tdep_stash_frame()
38 rs->reg[DWARF_CFA_REG_COLUMN].val, in tdep_stash_frame()
39 rs->reg[DWARF_CFA_OFF_COLUMN].val, in tdep_stash_frame()
41 rs->reg[RBP].where, rs->reg[RBP].val, DWARF_GET_LOC(d->loc[RBP]), in tdep_stash_frame()
42 rs->reg[RSP].where, rs->reg[RSP].val, DWARF_GET_LOC(d->loc[RSP])); in tdep_stash_frame()
50 && (rs->reg[DWARF_CFA_REG_COLUMN].where == DWARF_WHERE_REG) in tdep_stash_frame()
51 && (rs->reg[DWARF_CFA_REG_COLUMN].val == RBP in tdep_stash_frame()
52 || rs->reg[DWARF_CFA_REG_COLUMN].val == RSP) in tdep_stash_frame()
53 && labs(rs->reg[DWARF_CFA_OFF_COLUMN].val) < (1 << 29) in tdep_stash_frame()
55 && (rs->reg[RBP].where == DWARF_WHERE_UNDEF in tdep_stash_frame()
[all …]
/external/libunwind/src/ptrace/
D_UPT_access_reg.c41 _UPT_access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, in _UPT_access_reg() argument
48 …Debug(16, "using pokeuser: reg: %s [%u], val: %lx, write: %d\n", unw_regname(reg), (unsigned) reg,… in _UPT_access_reg()
51 Debug (16, "%s <- %lx\n", unw_regname (reg), (long) *val); in _UPT_access_reg()
55 if ((unsigned) reg - UNW_IA64_NAT < 32) in _UPT_access_reg()
60 mask = ((unw_word_t) 1) << (reg - UNW_IA64_NAT); in _UPT_access_reg()
88 switch (reg) in _UPT_access_reg()
139 reg = UNW_IA64_AR_BSP; in _UPT_access_reg()
230 if ((unsigned) reg >= ARRAY_SIZE (_UPT_reg_offset)) in _UPT_access_reg()
245 ptrace (PTRACE_POKEUSER, pid, (void*) (uintptr_t) _UPT_reg_offset[reg], (void*) *val); in _UPT_access_reg()
249 …ug(16, "ptrace PEEKUSER pid: %lu , reg: %lu , offs: %lu\n", (unsigned long)pid, (unsigned long)reg, in _UPT_access_reg()
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir.cpp96 imm.reg.type = type; in getImmediate()
221 memset(&reg, 0, sizeof(reg)); in Value()
222 reg.size = 4; in Value()
227 reg.file = file; in LValue()
228 reg.size = (file != FILE_PREDICATE) ? 4 : 1; in LValue()
229 reg.data.id = -1; in LValue()
244 reg.file = lval->reg.file; in LValue()
245 reg.size = lval->reg.size; in LValue()
246 reg.data.id = -1; in LValue()
260 LValue *that = new_LValue(pol.context(), reg.file); in clone()
[all …]
/external/google-breakpad/src/common/
Ddwarf_cfi_to_module.cc178 unsigned reg = i; in RegisterName() local
179 if (reg == return_address_) in RegisterName()
183 if (reg < register_names_.size() && !register_names_[reg].empty()) in RegisterName()
184 return register_names_[reg]; in RegisterName()
186 reporter_->UnnamedRegister(entry_offset_, reg); in RegisterName()
188 sprintf(buf, "unnamed_register%u", reg); in RegisterName()
192 void DwarfCFIToModule::Record(Module::Address address, int reg, in Record() argument
206 entry_->initial_rules[RegisterName(reg)] = shared_rule; in Record()
209 entry_->rule_changes[address][RegisterName(reg)] = shared_rule; in Record()
212 bool DwarfCFIToModule::UndefinedRule(uint64 address, int reg) { in UndefinedRule() argument
[all …]
/external/libunwind/src/ia64/
DGregs.c31 linux_scratch_loc (struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr) in linux_scratch_loc() argument
40 switch (reg) in linux_scratch_loc()
46 *nat_bitnr = (reg - UNW_IA64_NAT); in linux_scratch_loc()
52 addr += LINUX_SC_GR_OFF + 8 * (reg - UNW_IA64_GR); in linux_scratch_loc()
56 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR); in linux_scratch_loc()
78 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR); in linux_scratch_loc()
90 if (unw_is_fpreg (reg)) in linux_scratch_loc()
91 return IA64_FPREG_LOC (c, reg); in linux_scratch_loc()
93 return IA64_REG_LOC (c, reg); in linux_scratch_loc()
101 if ((unsigned) (reg - UNW_IA64_NAT) < 128) in linux_scratch_loc()
[all …]
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_sanity.c322 struct reg { struct
334 static struct reg regs[ARRAY_SIZE(reg_names)+1]; argument
335 static struct reg scalars[512+1];
336 static struct reg vectors[512*4+1];
370 static int find_or_add_value( struct reg *reg, int val ) in find_or_add_value() argument
374 for ( j = 0 ; j < reg->nvalues ; j++) in find_or_add_value()
375 if ( val == reg->values[j].i ) in find_or_add_value()
378 if (j == reg->nalloc) { in find_or_add_value()
379 reg->nalloc += 5; in find_or_add_value()
380 reg->nalloc *= 2; in find_or_add_value()
[all …]
/external/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3_print.c100 static void print_reg_name(struct ir3_register *reg) in print_reg_name() argument
102 if ((reg->flags & (IR3_REG_FABS | IR3_REG_SABS)) && in print_reg_name()
103 (reg->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))) in print_reg_name()
105 else if (reg->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT)) in print_reg_name()
107 else if (reg->flags & (IR3_REG_FABS | IR3_REG_SABS)) in print_reg_name()
110 if (reg->flags & IR3_REG_IMMED) { in print_reg_name()
111 printf("imm[%f,%d,0x%x]", reg->fim_val, reg->iim_val, reg->iim_val); in print_reg_name()
112 } else if (reg->flags & IR3_REG_ARRAY) { in print_reg_name()
113 printf("arr[id=%u, offset=%d, size=%u", reg->array.id, in print_reg_name()
114 reg->array.offset, reg->size); in print_reg_name()
[all …]
/external/wpa_supplicant_8/src/wps/
Dwps_registrar.c194 static int wps_set_ie(struct wps_registrar *reg);
198 static void wps_registrar_remove_pin(struct wps_registrar *reg,
202 static void wps_registrar_add_authorized_mac(struct wps_registrar *reg, in wps_registrar_add_authorized_mac() argument
209 if (os_memcmp(reg->authorized_macs[i], addr, ETH_ALEN) == 0) { in wps_registrar_add_authorized_mac()
215 os_memcpy(reg->authorized_macs[i], reg->authorized_macs[i - 1], in wps_registrar_add_authorized_mac()
217 os_memcpy(reg->authorized_macs[0], addr, ETH_ALEN); in wps_registrar_add_authorized_mac()
219 (u8 *) reg->authorized_macs, sizeof(reg->authorized_macs)); in wps_registrar_add_authorized_mac()
223 static void wps_registrar_remove_authorized_mac(struct wps_registrar *reg, in wps_registrar_remove_authorized_mac() argument
230 if (os_memcmp(reg->authorized_macs, addr, ETH_ALEN) == 0) in wps_registrar_remove_authorized_mac()
239 os_memcpy(reg->authorized_macs[i], reg->authorized_macs[i + 1], in wps_registrar_remove_authorized_mac()
[all …]

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